Tool/software:
Is there a spec for the amount of jitter the input clock to a DPLL can withstand before it loses lock?
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Tool/software:
Is there a spec for the amount of jitter the input clock to a DPLL can withstand before it loses lock?
Hello Nigel,
This thread has been reassigned to the correct HW engineer.
Best,
Josue
No.
The PLL is too complex to answer in this way.
Are you seeing something funny?
Kevin