Hi,
In our design, we planned to use the GPMC bus to exchange datas between the DM8148 and our FPGA. We configured the GPMC in NOR mode for synchronous single read and write accesses and with the datas multiplexed with the lower 16 bits of addresses.
Unfortunately, writing to the base address we set (0x1000000), we are'nt able to have the data present on the bus. According to what we grabbed with a scope (see attach picture) every control signal behaves as expected but the "lower 16 bits" are not displaying the datas we would like to write during the WE active period...
Here's the GPMC register values we set :
writel(0x00000008, &gpmc_cfg->sysconfig);
writel(0x00000000, &gpmc_cfg->irqstatus);
writel(0x00000000, &gpmc_cfg->irqenable);
writel(0x000001F1, &gpmc_cfg->timeout_control);
writel(0x00000012, &gpmc_cfg->config);
GPMC_CONFIG1_i 0x28401200
GPMC_CONFIG2_i 0x40500
GPMC_CONFIG3_i 0x20201
GPMC_CONFIG4_i 0x4030503
GPMC_CONFIG5_i 0x40405
GPMC_CONFIG6_i 0x40001C0
GPMC_CONFIG7_i 0xF41
for i = 0 as we use only CS[0] for now... Other CS are disabled...
And here is a picture of what we observe on the bus when writing datas "0xFFFFFFFF" at address "0x1000000"
D13 = CS[0]
D12 = ADV_ALE_n
D11 = GPMC_WE
D[7..0] = GPMC_AD[7..0]
As this is two 16 bits access, adresses seems to be ok (0x0 and 0x1) under the ADV_ALE signals but we would have expect bits 7 to 0 to change for 0xFF during the active period of the WE signal (D11 active low) as the data we would like to write is all "F"...
Is someone have a hint for us...? It probably has something to do with the GPMC register config but as far as we know, the whole thing seems ok for us...?!
Regards!
Seb