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DM8148/C6A8148 and DDR3 decoupling

M.A.M
Expert 8805 points

Hi,

The two DDR3 interfaces are recommended to be decoupled with 70 high-speed bypass capacitors (on 1.5V rail) in the datasheet Table 8-69. High-Speed Bypass Capacitors.

- Would it be enough with 35 caps if only one of the DDR3 interfaces is used?

(The configuration is to have two 16-bit DDR3 devices on that 32-bit port.)

/Magnus

  • 0
    TI__Intellectual 1610 points

    My recommendation is to keep the caps.  The two EMIFs share a common power supply.  Without the second interface, placement of the 35 caps for the other EMIF should not be difficult and it will give more power margin to the other interface.

    -Mike

  • 0 in reply to Michael Shust
    Prodigy 195 points

    Hi,

    There are tools available which can simulate and optimize the power delivery network (PDN) impedance over frequency. These tools take parameters like decoupling capacitor value/type/placement, PCB build up, via structure and power plane geometry into account. The designer will then have the freedom to optimize decoupling capacitor selection and placement versus performance and cost.

    I prefer this approach rather than a specification of xx amount of yy nF decaps in a given geometry. Examples of specific PDN designs could still be given in application notes or reference designs :-)

    Best regards,

    Michael

  • 0 in reply to Michael Iversen
    Prodigy 10 points

    HI Michael

     

    I am the customer that made Magnus post the question.

    Your right there are tools and the best think would be to do simulation.

    Beside the tool it requires that TI deliver a fuld AC model of what these supply pins draw of current as a function of frequency. TI do not even supply simple IBIS models, so I guess a dynamic supply model is way out of reach.

    Even if TI did supply the model I would have to buy the tool, as far as I now the pricing of these tools is decades out of our tool budget..

    /Peter