Hi,
How do TI recommend the placing of decoupling capacitors on the underside of the C6678 0.8mm pitch BGA?
The hardware design guide says: "TI recommends placing decoupling capacitors immediately next to the BGA vias, using the interior BGA space and at least the corners of the exterior." Of course this doesn't say how you recommend doing it!
The C6678 EVM does this by sharing through-hole vias between pads, which leaves room to fit decoupling capacitors. However, the EVM removes lots of vias. In some cases, 9 BGA pads are tracked together on the component side and only two vias join this track to the power/gnd plane.
Is this recommended by TI? It worries to me to see so many pads sharing a via.
cheers,
Richard