TDA4VM-Q1: cosult about ddr bandwidth

Hi,

There are multiple factors which can impact bandwidth. 

Here is one example using memory density and temperature:

An LPDDR4 part with 16Gbit channel density will require a refresh cycle time of 380 ns. At high temperature, the DDR controller will need to send (on average) a refresh command every 975 ns. This means that for a 975 ns interval, 380 ns will be spent waiting on the LPDDR4 to refresh its content. This translates to ~ 39% loss alone (not including loss due to overhead of opening / closing pages, nature of traffic, other background tasks such as periodic training, ECC (if enabled) , etc. ). 

Whereas a smaller density memory will have a smaller refresh cycle time (less time waiting for memory to refresh its content) and cooler temperatures will require less frequent refresh commands.

My understanding is that around 40% is typical - though I'll have to see if a colleague can confirm this.

As a side note, should the theoretical bandwidth be ~ 14.9 GB/s at 3733 MT/s? 

xie jc said:

1866 MHz, the theoretical bandwidth should reach 16.6 GB/s.

Regards,
Kevin