PROCESSOR-SDK-J721S2: TDA4VE-Q1,J721S2 about DSI output Resolution

Hi,

The Expert assigned to this in attending a workshop this week. Kindly expect a delay in the response.

Best Regards,
Sudheer

Hi Terry,

Can you please try with below changes? 

Width = 3840

Height = 720

hfp = 344

hsw = 144

hbp = 547

vfp = 6

vsw = 2

vbp = 72

pixel clock = 117000000

Regards,

Brijesh

Hi Brijesh,

We tried to modify this timings , but DSS initialization failed after the modification.

Do you have any ideas?

The error LOG as below:

[Tue Nov 26 15:15:35.701 2024] [MCU2_0]     13.017584 s: | I | default | src/drv/dctrl/dss_dctrlApi.c @ Line 1182:

[Tue Nov 26 15:15:35.707 2024] [MCU2_0]     13.017615 s: | I | default | Set VP parameters IOCTL failed

[Tue Nov 26 15:15:35.714 2024] [MCU2_0]     13.017660 s: | I | default | DSS DUAL DISPLAY: ERROR: Dctrl default init failed !!!

[Tue Nov 26 15:15:35.722 2024] [MCU2_0]     13.017693 s: | I | default | DSS DUAL DISPLAY: Init ... Done !!!

thanks

Hi Terry,

Looking at the driver code, it shouldn't fail, so can you please use CCS and see where it is failing? 

Regards,

Brijesh

Hi Brijesh,

what is CCS ?

We do not know how to print log at dsitx_sanity.c.

It should fail at "if (obj->vbp > (0x3FU))"

//

psdk_rtos\pdk_j721s2_08_04_00_20\packages\ti\drv\dss\src\csl\dsi\src\dsitx_sanity.c

/**

 * Function to validate struct VideoSize

 *

 * @param[in] obj pointer to struct to be verified

 * @returns 0 for valid

 * @returns CDN_EINVAL for invalid

 */

uint32_t DSITX_VideoSizeSF(const DSITX_VideoSize *obj)

{

    uint32_t ret = 0;

    if (obj == NULL)

    {

        ret = CDN_EINVAL;

    }

    else

    {

        if ((obj->vsa < (0x1U)) || (obj->vsa > (0x3FU)))

        {

            ret = CDN_EINVAL;

        }

        if (obj->vbp > (0x3FU))

        {

            ret = CDN_EINVAL;

        }

        if (obj->vfp < (0x1U))

        {

            ret = CDN_EINVAL;

        }

        if ((obj->vact < (0x1U)) || (obj->vact > (0x1FFFU)))

        {

            ret = CDN_EINVAL;

        }

        if (obj->hsa > (0x3FFU))

        {

            ret = CDN_EINVAL;

        }

        if (obj->hfp > (0x7FFU))

        {

            ret = CDN_EINVAL;

        }

        if (obj->rgb > (0x7FFFU))

        {

            ret = CDN_EINVAL;

        }

        if (obj->blkEolPacket > (0x7FFFU))

        {

            ret = CDN_EINVAL;

        }

        if (obj->blkLineEventPacket > (0x7FFFU))

        {

            ret = CDN_EINVAL;

        }

        if (obj->blkLinePulsePacket > (0x7FFFU))

        {

            ret = CDN_EINVAL;

        }

    }

    return ret;

}

Regards,

ok, can you please rearrange vfp and vbp?

vfp = 18

vsw = 2

vbp = 60

Regards,

Brijesh

Hi Brijesh,

We will try to rearrange vfp and vbp tomorrow.

Under what circumstances do you think it would happen that the DSI_VID_MODE_STS register would read 0x04(ERR_MISSING_HSYNC)?

Can you help confirm  link as below? Is it the same problem?? Could you provide a patch file that fixes this issue?

https://sir.ext.ti.com/jira/si/jira.issueviews:issue-html/EXT_EP-11865/EXT_EP-11865.html

thanks

Hi Terry,

Yes, this is the same issue and the fix is to adjust timing only. 

Regards,

Brijesh

Hi Brijesh,

Do we need to upgrade the driver to PROCESSOR_SDK_10.01.00?

We need to be able to more freely adjust video timing,Because these timing requirement come from the monitor spec.

thanks.

Hi Terry,

No, even in SDK10.1, this is not going to be fixed.  We need to adjust timing based on the lane speed and other parameter requirement. 

Regards,

Brijesh

Hi Brijesh,

Thanks for your reply.

If the timing(such as BackPorch、FrontPorch ) is adjusted excessively, the image displayed on the monitor will not be centered.

thanks.

Hi Terry,

No, i really doubt it would affect the output, as normally what is important is frame size, which is not changing. 

Regards,

Brijesh

Hi Brijesh,

Depends on whether there is an scaler IC between TDA4 and the monitor, If there is no scaler IC to retiming for LCD ,then adjust the Back Porch or Front Porch, and the position of the image on the display will also be offset.

We have tested this because the monitor we are using now does not have a scaler IC .

thanks.

Hi Brijesh,

Sorry,I accidentally clicked to solve the problem.

for DSI, they are just part of the blanking, isn't it? 

Because there are sync START and sync end and DE  packets on dsi protocol  ,serdes can calculate BP and FP based on these packets and retransmit the OLDI output or DPI output at the deserializer side.

It is not like CSI which only has Frame valid and Line valid  packets.

e2echina.ti.com/.../swpa225_5B00_1_5D00_.pdf

thanks

Hi Brijesh,

We can not see TX output after rearrange vfp and vbp.

(Same as : When 3840x720x30Hz,we can get value:0x04 from the DSI_VID_MODE_STS Register.)

8004.Log__20241126.log

Could you please help to check the log.

if any fail log about DSS DSI at booting ?

We can run application after boot done. And press "p" to see  DISPLAY1 of DrawGL_Graph. Had ran #executions =       2164.

Regards,

Hi Brijesh,

We try to rearrange vfp and vbp. And get the same result as "When 3840x720x30Hz,we can get value:0x04 from the DSI_VID_MODE_STS Register".

Could you help to check the log.6087.Log__20241126.log

If any fail information about DSS dsi at booting.

Regards,

Thanks for the update. What's the final fix/updated timing values?

Hi Brijesh,

dsi_params.laneSpeedInKbps=4480*750*60*6/1000;

prm.display[1].timings.width          = 3840U;

prm.display[1].timings.height        = 720U;

prm.display[1].timings.hFrontPorch       = 432U;

prm.display[1].timings.hBackPorch        = 64U;

prm.display[1].timings.hSyncLen   = 144U;

prm.display[1].timings.vFrontPorch       = 26;

prm.display[1].timings.vBackPorch        = 2;

prm.display[1].timings.vSyncLen    = 2;

prm.display[1].timings.pixelClock  = 4480*750*60ULL

thanks

Thanks Terry, that matches with my equation. 

lane speed = pixel clock * 24 / number of lanes. 

Regards,

Brijesh