Tool/software:
Question setting up the ALE table and configuration of the Ethernet Subsystem of the AM335x Sitara Processor
This is a section from the data sheet describing how to set up dual mac mode with seperation (at the switch) between the host/port1, host/port2 networks. This works.
14.3.2.10.2 Dual Mac Mode
When operating in dual mac mode the intention is to transfer packets between ports 0 and 1 and ports 0
and 2, but not between ports 1 and 2. Each CPGMAC_SL appears as a single MAC with no bridging
between MAC’s. Each CPGMAC_SL has at least one unique (not the same) mac address.
Dual mac mode is configured as described below:
- Set the ale_vlan_aware bit in the ALE_Control register. This bit configures the ALE to process in vlan
aware mode.The CPSW_3G vlan aware bit (vlan_aware in CPSW_Control) determines how packets
VLAN’s are processed on CPGMAC_SL egress and does not affect how the ALE processes packets or
the packet destination. The CPSW_3G vlan aware bit may be set or not as required (must be set if
VLAN’s are to exit the switch).
- Configure the Port 1 to Port 0 VLAN
Add a VLAN Table Entry with ports 0 and 1 as members (clear the flood masks).
Add a VLAN/Unicast Address Table Entry with the Port1/0 VLAN and a port number of 0. Packets
received on port 1 with this unicast address will be sent only to port 0 (egress). If multiple mac addresses
are desired for this port then multiple entries of this type may be configured.
- Configure the Port 2 to Port 0 VLAN
Add a VLAN Table Entry with ports 0 and 2 as members (clear the flood masks).
Add a VLAN/Unicast Address Table Entry with the Port2/0 VLAN and a port number of 0. Packets
received on port 2 with this unicast address will be sent only to port 0 (egress). If multiple mac addresses
are desired for this port then multiple entries of this type may be configured.
- Packets from the host (port 0) to ports 1 and 2 should be directed. If directed packets are not desired
then VLAN with addresses can be added for both destination ports.
- Select the dual mac mode on the port 0 FIFO by setting tx_in_sel[1:0] = 01 in P0_Tx_In_Ctl. The
intention of this mode is to allow packets from both ethernet ports to be written into the FIFO without
one port starving the other port.
- The priority levels may be configured such that packets received on port 1 egress on one CPDMA RX
channel while packets received on port 2 egress on a different CPDMA RX channel.
We are looking for a similar description for a dual mac setup where both ports are on the same subnet and all ports see all traffic. We need this because we’d like to use a hub function rather than a switch function allowing all packets to be presented to the HOST, MAC1 and MAC2. The design daisy chains multiple AM335X processors together with other boards.
