Hi,
I am using the GPMC bus to transfer datas between the DM8148 and my FPGA. The bus is used in NOR type with single synchronous access. The lower parts of the addr [15:0] is multiplexed with the data bus. I'm using only CS0 and the config is as followed :
writel(0x00000008, &gpmc_cfg->sysconfig);
writel(0x00000000, &gpmc_cfg->irqstatus);
writel(0x00000000, &gpmc_cfg->irqenable);
writel(0x000001F1, &gpmc_cfg->timeout_control);
writel(0x00000012, &gpmc_cfg->config);
GPMC_CONFIG1 0x28401200
GPMC_CONFIG2 0x20300
GPMC_CONFIG3 0x10100
GPMC_CONFIG4 0x2010301
GPMC_CONFIG5 0x20203
GPMC_CONFIG6 0x10101C0
GPMC_CONFIG7 0xF41
Doing read or write accesses to the memory location where my FPGA is mapped seems to work fine except for the upper address bits which are on bits [27:17]. No matter what the base address or the mask is and if it is a write or a read access, those upper bits are always stuck to '1' (bus equal to "3FF").
As an example :
CS0 base addr = 0x1000000 and Mask = 16Mb
Writing to 0x1000000 a 32bits data = 0xFFFFFFFF leads to ADDR/DATA [15:0] = 0x0 during ALE and 0xFFFF during WE but ADDR[27:17] = 0x3FF....
Writing to addr = 0x100000 should have displayed ADDR/DATA[15:0] = 0x0 and ADDR[27:17] = 0x40...
Can someone help me with this...?!
Regards!
Seb
