Connecting a large NAND Flash memory device to the GPMC interface of the DM8168

Galadriel said:

The maximum supported memory size of 2Gb per CS of the GPMC does not apply to NAND Flash, right?

512MB is the total addressable memory of the GPMC (i.e. for all chip selects combined).  NAND does not use address lines from the GPMC so you will only need to use a tiny address space from the GPMC perspective to write to a huge NAND space since all the addressing is done through the NAND protocol.  So to be clear you are NOT limited to only 512 MB in terms of the NAND size.

Galadriel said:

According to section "25.7.3 NAND" of SPRUGX8 document, any NAND Flash enumerated in the supported devices table can be used. Is it true for ALL DM816x processors?

Yes.  There's no difference in GPMC between the various DM816x devices.

Galadriel said:

For devices of 8Gb or larger, more than one CE# is available. Are those devices "CE don’t care devices" anyway? How CE# signals should be connected to the DM8168?

You need to look at the memory data sheet.  For example, is it a stacked die memory where there are multiple NAND flashes in a single package?  If so, you probably need to hook each chip select of the NAND to a unique chip select on the DM816x.  In general I don't see why they would bother putting on extra chip selects if they were not needed.

Thanks Brad,

The device we are looking at is the Micron MT29F8G16 http://download.micron.com/pdf/datasheets/flash/nand/2_4_8gb_nand_m49a.pdf. It is a quad-die stack with two CE# and two R/B# signals. According to the datasheet:

• CE# and CE2# each control independent 4Gb arrays. CE2# functions the same as CE# for its own array.
• R/B# and R/B2# can be tied together, or they can be used separately to provide independent indications for each 4Gb section.
• Bit 1, on the fifth array addressing cycle, is used for the die address boundary, where: “0” = 0Gb–2Gb devices; “1” = 2Gb–4Gb devices.

It means that for this particular device, we must connect CE# to GPMC_CS[0] and CE2# to GPMC_CS[1].

1. Shall we consider this device as two seperate NAND Flashes?
2. Would it be better to connect both R/B# and R/B2# to GPMC_WAIT0, or to connect R/B# to GPMC_WAIT0 and R/B2# to GPMC_WAIT1?

Best regards,
Julie

Thanks :-)