DRA829J-Q1: Issue with DDR initialization (sporadic data change in memory / on the bus)

Part Number: DRA829J-Q1

Tool/software:

Dear TI-Team,

couple of our custom boards based on DRA829JMTGBALFRQ1 and Nanya NT6AN512T32AC have a problem with DDR initialization (u-boot):

After DDR initialization sequence is done, we can observe in the debugger dump window that memory content is changing sporadically. Also if we try to write pattern to the memory, only 2 high bytes out of each 4 bytes word are changed to the desired value.

What is interesting, if we perform MCU R5F soft reset (or via input pin) and u-boot repeat initialization sequence (including DDR controller), everything works reliably. And most of the produced till now boards works reliably with the same code.

Could you please give a vector where to search a possible root cause.

Thanks,
Dmitry

P.S. We also tried to use CMM scripts (for Lauterbach debugger) previously provided by TI to initialize system and behavior is the same - sporadic data change in memory and only half of each word is writable.

  • Hi Dmitry,

    So the issue only occurs out of a cold boot? (If you were to issue the MCU R5F soft reset several times, would the issue ever occur?)

    You mention that a few boards show the issue. Does this imply that many boards do not show the issue? Or have only a few boards been tested?

    After the issue occurs, are you able to load and execute the attached binary from Code Composer Studio and provide the CCS console output? (please load / execute from R5 core).

    0083.tda4x_lp4_debug.zip

    Regards,
    Kevin

  • Hi Kevin,

    yep, the issue appears only during cold boot, then it was tried to make multiple soft resets and starting from the first one DDR was always stable.

    Only few boards have been produced till now (~50) and 3 of them are affected.

    We do not use CCS, rather TRACE32, but I will try to load provided binary next days and let you know about results.

    Regards,
    Dmitry