I understand the C6678 explicitly states there is a power down requirement and that long term exposure to an environment in which one of the supplies is not present will affect the long term reliability of the device. Having said that, I have an application where the input power to the design may be removed without notice and there may not be enough time to properly sequence down the supplies. It would be preferable when this happens to simply disable all power supplies simultaneously. In this situation, there would not be "long term exposure" but even though all rails would be disabled at the same time, they would likely fall at different rates. This case (where power is removed without warning) would happen very infrequently but could happen. Would you be able to comment on this scheme? While I understand there may not be guaranteed long term reliability under this scenario, I would appreciate any comment,feedback or thoughts related to this.
Thanks,
John
From the C6678 datasheet
7.2.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a
large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the
supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail,
POR should transition to low to prevent over-current conditions that could possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term
exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability
of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an
active reset can also affect long term reliability.
