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SK-AM62P-LP: AM62P PMIC connection for Low power support

Jhon Q
Prodigy 165 points
Part Number: SK-AM62P-LP
Other Parts Discussed in Thread: AM62P

Tool/software:

Hi,

Referring to the below implementation from the SK-AM62P-LP EVK (PROC164E1-1) schematics:

1. Is it correct to assume that for supporting low power mode, should U85.1 SEL = LOW?

2. If so, in case SEL= HIGH (Low power mode is not supported), why is PMIC_LPM_EN0 connected via buffers & FET to PMIC pin 17?

Thank you for your support,

Jhon

  • 0
    TI__Guru**** 155889 points

    Hello Jhon, 

    Thank you for the query.

    Let me check internally and assign to the expect.

    Please expect delay in response due to the US holidays.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Mastermind 19976 points

    Hi Jhon,

    Thank You for using E2E. The connections between SoC and PMIC depend on the low power modes requirements (if any). The U85 MUX will most likely not needed in your application. This MUX was placed in the EVM so we could test all the SoC low power modes with the same PMIC orderable. 

    Are you planning to use "Partial IO" or "IO+DDR" low power mode?

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 165 points

    Hi,

    I would like to have the option to use "Partial IO" or "IO+DDR" low power modes.

    What state U85 should be set to?

    can you refer to Q1,2 above?

    thank you,

    Jhon

  • 0 in reply to Jhon Q
    TI__Mastermind 19976 points

    Hi Jhon,

    Here is the information on how to configure the U85 MUX in the AM62P EVM. Let us know if you have any questions. 

    For "Partial IO" low power mode:

    • J12 uninstalled/open (U85 SEL pin = high). In this configuration PMIC_LPM_EN0 drives the PMIC enable pin to turn-OFF the PMIC when entering "RTC only low power mode". Only external discrete devices are kept ON (i.e. VDD_CANUART, VDDSHV_CANUART). 

    For "IO + DDR" low power mode:

    • J12 installed (U85 SEL pin = low). In this configuration PMIC_LPM_EN0 drives the PMIC_nsleep (GPIO4) to turn-OFF specific PMIC rails (i.e VDD_CORE, VDDA1V8). 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 165 points

    Hi ,

    Thank you for your reply.

    1. To be aligned with AM62P datasheet terms, can you verify these are the 2 power modes:

    a. "RTC only" = "Partial IO support for CAN/GPIO/UART wakeup"

    b.  "RTC + DDR" = "I/O Only + DDR in Self Refresh for Suspend to RAM"

    2. Is "DeepSleep" mentioned in the datasheet a different, 3rd low power mode or it is one of the above mode? if it differs, what is the difference between "RTC + DDR" and "DeepSleep"?

    3. For which power modes do VDD_CANUART, VDDSHV_CANUART need to be supplied from an always on power supply?

    4. Is it possible to support both "RTC only", "RTC + DDR" modes in design via GPIO control in runtime or does it require separate device tree? in there any benefit/sense in doing so?

    5. Which modes are implemented in AM62P SW and what is the default low power mode?

    Thank you for your clarification,

    Jhon

  • 0 in reply to Jhon Q
    TI__Mastermind 19976 points

    Hi Jhon,

    That is correct, AM62P does not have "RTC only" or "RTC+DDR" low power mode. It has "Partial IO" and "IO+DDR". Sorry for the confusion here.

    • "Partial IO"  is the low power mode that requires supplying the CANUART rails (VDD_CANUART, VDDSHV_CANUART) with always-ON discrete devices. The remaining low power modes can be supported with the PMIC.

    • To support "IO+DDR", the PMIC turns-OFF the CORE rails and the 1.8V analog. DDR in self-refresh.  

     

    You can find more detailed information about each of the AM62P low power modes (including the wakeup resources, use cases, power domains, etc) in the Technical Reference Manual, section 6.2.4 Power Modes.. Here is the link: https://www.ti.com/lit/pdf/spruj83

     

    Let us know if you have additional questions. 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 165 points

    Hi

    Thank you for your prompt reply.

    1. Can you advise on Q4 above?

    2. We wish to support also DeepSleep mode which according to RM section 6.2.4, is a 3rd mode. should the implementation be as for "IO + DDR" low power mode U85 SEL pin = low so that PMIC_LPM_EN0 drives the PMIC_nsleep (GPIO4)? or can DeepSleep mode be supported also if U85 SEL pin = high?

    thank you for your support,

    Jhon

  • 0 in reply to Jhon Q
    TI__Mastermind 19976 points

    Hi Jhon,

    Please find the answers below and let us know if you have any additional questions.

    1. Supporting "IO+DDR" and "Partial IO" with the same PMIC GPIO would require to modify the PMIC configuration before entering the low power mode. This might also require a new PMIC orderable with custom OTP settings. Please note PMIC register settings go back to the default values after power cycle. The idea of supporting "Partial IO" low power mode with the PMIC enable pin (by turning-OFF the entire PMIC) is to achieve the lowest power consumption. 
    2. To support DeepSleep low power mode, you can follow the same hardware configuration as "IO+DDR" where the processor PMIC_LPM_EN signal controls the PMIC GPIO.  

    Thanks,

    Brenda