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TMDS64EVM: Dynamic change of CPU frequency

Jakub Grad
Intellectual 650 points
Part Number: TMDS64EVM

Tool/software:

Hi

I have a peace of code for DCC0 peripheral and I want to test it by changing SYSCLK frequency. If I understand correctly after changing frequency ESM interrupt should be triggered. I tried play with that by /sys/devices/system/cpu/cpufreq/ but unfortunately this directory is empty. Also I tried to this with k3conf tool by typing command  k3conf set clock 16 6 25000000 but frequency stays the same as before. According to the documentation, the clock source DEV_DCC0_DCC_CLKSRC6_CLK represents Main Sysclk0. This SYSCLK0 is CPU frequency at which Linux OS is running, if I understood correctly.

root@puma:~# k3conf set clock 16 6 25000000
|--------------------------------------------------------------------------------|
| VERSION INFO |
|--------------------------------------------------------------------------------|
| K3CONF | (version v0.1-88-g982f5c2 built Mon Nov 4 11:02:54 AM UTC 2024) |
| SoC | AM64x SR2.0 |
| SYSFW | ABI: 3.1 (firmware version 0x0008 '8.6.4--v08.06.04 (Chill Capybar)') |
|--------------------------------------------------------------------------------|

|-------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|-------------------------------------------------------------------------------------|
| 16 | 0 | DEV_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 |
| 16 | 1 | DEV_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 80000000 |
| 16 | 2 | DEV_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 133333333 |
| 16 | 3 | DEV_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 250000000 |
| 16 | 4 | DEV_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 25000000 |
| 16 | 5 | DEV_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 |
| 16 | 6 | DEV_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 500000000 |
| 16 | 7 | DEV_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 60000000 |
| 16 | 8 | DEV_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 25000000 |
| 16 | 9 | DEV_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 0 |
| 16 | 10 | DEV_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 |
| 16 | 11 | DEV_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 |
| 16 | 12 | DEV_DCC0_VBUS_CLK | CLK_STATE_READY | 125000000 |
|-------------------------------------------------------------------------------------|

  • 0
    TI__Guru* 87095 points

    Hello Jakub,

    What core are you using to control the DCC? Are you using a TI driver to do it?

    If you are using a TI driver, we can contact the development team to see how they test driver functionality for the DCC. I suspect that using the k3conf tool to modify clock frequency would NOT lead to the error states you are looking for.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Intellectual 650 points

    Hi Nick

    I'm using R5 Core 0. Yes, I'm using TI driver to control DCC on R5 side: API
    Why k3conf used in this scenario would not lead to error states? If DCC counters are programmed according to specific clock frequency, changing clock frequency externally (by k3conf) should trigger the error, I think.

    Regards,

    Jakub