EMIFA Asynchronous 16-bit Iinterface OMAPL138 to Actel IGLOO FPGA

Hi Barry,

See section 11.5.10 of the OMAP-L138 TRM for a description of the pin-by-pin multiplexing scheme.  This scheme does indeed allow you to repurpose unused EMIFA pins for use by a differenly interface like MMCSD.  The EMIFA peripheral behavior itself will be the same despite any pin multplexing choices for the address lines.

Although I'm not familar with Actel FPGAs, I don't see why they couldn't be used tlike the Xilinx FPGA example to implement a FIFO interface that does not require use of the EMIFA address lines.

Regards,

Brad

Hi Brad

Thanks for the prompt reply and the clarification. The interfaces can be active at the same time then  - interesting.

The prioritisation mechanism on the DSP would ensure only the emif or mmcsd access the lines on a per cycle basis (hence no bus contention).

The real issue is if the EMIF becomes active and the MMCSD0 card mistakes that as a MMCSD command.

MMCSD0_CMD line is muxed with EMA_A[22] and the MMCSD data lines are muxed with the other EMA_A[21:14].

If we used EMA_CS2 for example and always just wrote to the base address when making FPGA accesses (0x6000 0000) this may work then if:

1 :  The base address (0x6000 0000) never activates the MMCSD0_CMD line

2:  Not familiar with the MMCSD0 command protocol. If it supported  instructions  like block read which didn't require subsequent command inputs and simply clocked data out in sequence after reading the initial instruction. Think that could also cause a problem.

Does this sound reasonable ?

BR

Barry

Barry,

It is a manual process to assign a specific processor pin to module (eg. EMIFA or MMCSD) signal.  In most systems, the pin multiplexing is a static configuration programmed at boot time (i.e. a pin would either function as a EMIFA pin or a MMCSD pin for the duration of the application).  It is possible for software to manually switch the multiplexing of a pin from one module to another during device operation, however, care must be taken at the board level to prevent the issues that you bring up above.

For the FPGA FIFO example that you proposed, the EMIFA address lines are not required.  Therefore, the pins that would normally output an EMIF address can be programmed to instead output the MMCSD signals.  In this case, these pins will no longer be under the control of EMIFA and instead will be under the control of the MMCSD module.

-Brad

Hi Brad

Think the real issue lies in this bit  "the pins that would normally output an EMIF address can be programmed to instead output the MMCSD signals.  In this case, these pins will no longer be under the control of EMIFA and instead will be under the control of the MMCSD module."

Although the EMIFA address lines are not being used physically on the interface they will react - guess the ideal scenario would be to have the EMIFA configurable with 0 address lines (option available is for 8-bit and 16-bit).

Thanks for all the help Brad - am much the wiser for the inputs. Have a great weekend

BR

Barry

Barry,

If you program the pin mux registers to select MMCSD signals instead of EMIF address signals, the pins will NOT react to EMIFA address changes.  There is a multiplexor that sits in front of the drivers for the pins that allows only one of the multiplexed signals to propogate to the pin.  The non-selected output signals (EMIFA address in this case), get blocked at the input of this multiplexer and will have no control/effect on the external pins.

Regards,

Brad

Thanks for the clarification Brad

Thanks again

BR

Barry

PS Jason says Hi ..:)