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c5515 cannot boot from flash if put .cinit part to SDRAM

When i place the .cinit part to flash, i can boot successfully. But when i put the .cinit part to SDRAM, nothing happens, even no CPU clock. But i have such large amount of data in .cicnit that i cannot put all of them on flash.

Anyone can tell me why i have to put .cinit part in flash, and how to put them to SDRAM?

  • Hi Lihong,

    I suppose  you boot up from flash in both cases (.cinit in flash and .cinit in SDRAM). You will have to configure the EMIF SDRAM registers before the on-chip bootloader can put any code into SDRAM. When .cinit is in flash there is no problem as the EMIF is already configured to interface to the flash when bootloader starts code execution.

    You can put code segments directly into SDRAM while bootloading by inserting register configuration data while building the boot image using the hex55 utility. This information is used by the bootloader to configure peripherals before bootloading the image. Please see section 2.3 of "Using the TMS320C5535/34/33/32 Bootloader" (sprabl7.pdf) application note. 

    If you are using the C55x boot image generation utility, you can specify register configuration data in an optional  file while creating the flash boot image. I have attached an example file that changes PLL and SPI registers. You will have to modify this to specify EMIF SDRAM register and with appropriate values. Register 0xFFFF indicates a delay directive as mentioned in the above appnote.

    SIZE:	0x0A
    ADDRESS:	 0x1C1F
    CONTENT:	 0x0000
    ADDRESS:	 0x1C20
    CONTENT:	 0x8BB4
    ADDRESS:	 0x1C21
    CONTENT:	 0x8000
    ADDRESS:	 0x1C22
    CONTENT:	 0x0806
    ADDRESS:	 0x1C23
    CONTENT:	 0x0001
    ADDRESS:	 0xFFFF
    CONTENT:	 0x0040
    ADDRESS:	 0xFFFF
    CONTENT:	 0x0040
    ADDRESS:	 0x1C1F
    CONTENT:	 0x0001
    ADDRESS:	 0x3000
    CONTENT:	 0x0003
    ADDRESS:	 0xFFFF
    CONTENT:	 0x0100
    

    Regards,

    Sunil

  • Look at this topic

    http://e2e.ti.com/support/dsp/tms320c5000_power-efficient_dsps/f/109/p/132583/476535.aspx