TDA4VH-Q1: how to enable DDR INLINE_ECC for some areas.

Hello Tao,

https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j784s4/10_00_00_08/exports/docs/linux/Foundational_Components/U-Boot/UG-DDRSS-J7.html

Could you please make sure if enabling it for the complete DDR is functional?

Enabling partial ECC is not supported out of the box. Also what is the reason for enabling partial ECC. As per hardware design
even partial ECC enabling will take up 1/8th of entire DDR for ecc.

- Keerthy

1. I removed the last 2GB of memory in dts:
memory@80000000 {
device_type = "memory";
/* (16-2)=14G RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x03 0x00000000>;
};

2. The reason for enabling partial ECC：
We want to protect memory for low 2GB when performing high and low temperature tests.

I wonder if the above configuration is correct at the register level if I do ECC protection for the lower 2GB.

I modified the SBL code to support ECC protection for the first 14GB of DDR memory, and the register configuration is as follows:

Meanwhile I removed the last 2GB of memory in dts:
memory@80000000 {
device_type = "memory";
/* (16-2)=14G RAM */
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x08 0x80000000 0x03 0x00000000>;
};

When the SBL is started and after ECC configuration is complete, the first 14GB memory is written into the pattern through the UDMA:

The system is running without ECC errors.

Okay. Let me know if anything is needed from our side. Partial DDR inline ecc is not supported.

Best regards,

Keerthy