[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM624SIP: AM6254 LPDDR4 LENGHT/DELAY MATCHING

Paul Nwoko

Prodigy 105 points

Part Number: AM625

Tool/software:

Hi Ti Experts,

I'll like to know if it is compulsory to consider package pin delay when matching lpddr4 line.

Also, where can I get the package pin delay information for AM6254 SoC.

Thanks. looking forward to your response.

Regards,

Paul.

11 months ago

0 JJD 11 months ago

TI__Guru* 88450 points

Please refer to the AM62x DDR layout guidelines: https://www.ti.com/lit/pdf/sprad06

Regars,

James

0 Paul Nwoko 11 months ago in reply to JJD

Prodigy 105 points

Thank you James,

But I also like to know if the pin package delay can be ignored without issues?

expecting your response.

Regards,

Paul

0 Paul Nwoko 11 months ago in reply to Paul Nwoko

Prodigy 105 points

Also, should the pin package delay of the DDR chip in use be considered as well?

+1 JJD 10 months ago in reply to Paul Nwoko

TI__Guru* 88450 points

Pin package delay consideration should not be necessary. During the training process, there is per-bit deskew which can compensate for package length mismatches. As long as you match pin to pin on board according to the skews in the appnote, the training will take care of optimizing skews across byte lanes and ctrl/addr signals

Regards,

James

Processors

Processors forum

[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM624SIP: AM6254 LPDDR4 LENGHT/DELAY MATCHING