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TDA4VM: Can not access PCIE2_DAT0

Thomas Dorsch
Expert 2590 points
Part Number: TDA4VM

Tool/software:

Hi TI,

we have currently an issue with PCIE2_DAT0 on TDA4. We are using ti-uboot-2023.04 to bring the TDA4 until u-boot stage, which then loads and starts the firmware for mcu2-0.

The pcie module index 2 is configured to access memory of another board with TDA4 via PCIE2_DAT0 region.

The issue is, that I can not access PCIE2_DAT0 region from mcu2-0. Following summarizes what I have tried so far:

1. PCIE2_DAT0 memory is located within 48-bit address space. (0x4400000000)
The RAT unit of mcu2-0 is configured to map this memory region (0x4400000000) into ARMSS_RAT_REGION2 address range (0x10000000)
I connect CCS to mcu2-0, and use the memory browser to read from the mapped memory region (0x10000000).

Result: I get "?" in Memory Browser view and it looks that the TDA4 has crashed.

CCS Output: MAIN_Cortex_R5_0_0: Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.0.0.3178)
MAIN_Cortex_R5_0_0: Unable to determine target status after 20 attempts
MAIN_Cortex_R5_0_0: Failed to remove the debug state from the target before disconnecting.  There may still be breakpoint op-codes embedded in program memory.  It is recommended that you reset the emulator before you connect and reload your program before you continue debugging

2. Try to avoid any RAT configuration issues and using the A72 core to peek into PCIE2_DAT0 region:
I connect CCS to a72 and use memory browser to read from memory region 0x4400000000.

It just shows "?" (cannot read from that address) but this time, the TDA4 is not crashing like from R5.

Note: The "Memory View" is set to "CPU Memory View".

3. Same as 2, but this time I set Memory View of Memory Browser to "Physical Memory View".

Now I can see the data from the other board. (It works!)

The conclusion for me is, that the PCI configuration/access in general is working. But there is an general issue of accessing PCIE2_DAT0.

Can you please help me here? Our final goal is to access it from mcu2-0.

Thank you and best regards,
Thomas

  • 0
    TI__Mastermind 35272 points

    Hi Thomas,

    As a disclaimer, TI does not have software support for PCIe RTOS driver, and thus, no support for PCIe on R5F. TI only supports Linux driver hosted on the A72 core. So, although what you are attempting is not a full blown out driver implementation, it is uncharted territory. 

    You have mentioned U-Boot is in play, but when is the PCIe memory space accessed in both the case of using MCU2-0 to peek and A72 to peek at memory? Is it accessed in both cases after Linux has booted up and initialized the PCIe module, or is it stopped in U-Boot before going into Linux?

    Regards,

    Takuma

  • 0 in reply to Takuma Fujiwara
    Expert 2590 points

    Hi Takuma,

    thank you for your reply. Yes, I am aware of that. I'm not asking for support of how to configure the pcie module correctly, that a pci link is established between two pci modules (this is working).

    I think there is some issue on the path between any core (A72, mcu2-0) and PCIE2_DAT0. For that I need support.

    To answer your question: In all three scenarios, following is happening:

    1. u-boot is booting
    2. u-boot loads mcu2-0 firmware and starts mcu2-0 with it
    3. At this point, A72 is not doing anything. No linux is booted. It just idles in u-boot environment.
    4. mcu2-0 firmware initializes and configures serdes & pcie module
    5. mcu2-0 firmware establishes successfully a data link of pcie module with another board. (LTSSM reaches L0)
    6. At this point, I start to try to access PCIE2_DAT0 with CCS Memory Browser as described in my first post.

    As my 3. scenario in the first post shows, I can read/write successfully on PCIE2_DAT0 with memory browser (connected to A72), but with "physical memory view". So it's not a general issue with the pci module configuration.

    Therefore I think it's somehow the path between a core and PCIE2_DAT0.

    I'm not an TDA4 expert, but I guess that

    1. MPU configuration of R5
    2. RAT configuration of R5
    3. Firewall configuration
    4. QoS configuration

    are potential issues. Propably even more, which I simply dont know yet.

    My quick test, to simply use the A72 for PCIE2_DAT0 access has the background to eliminate 1 and 2 from that list.
    I hope you can help me here to solve that issue. I also hope that there is no general "silicon issue" which prevents the access.
    Thank you and best regards,
    Thomas

  • 0 in reply to Thomas Dorsch
    TI__Mastermind 35272 points

    Hi Thomas,

    For Linux, there is some mechanism to define some flags for the memory space like in this documentation: https://elinux.org/Device_Tree_Usage 

    I am not sure how this is handled for your code, but perhaps this is missing?

    Regards,

    Takuma