PROCESSOR-SDK-AM62X: Backward compatibility to GiCv2

Hello Simon Plantier

TYhank you for the query.

Let me check with the team internally.

Regards,'

Sreenivasa 

Hi Simon,

I don't see any reference of "v2' in the device tree (k3-am62-main.dtsi) you linked. The GIC uses v3 compatible there.

    gic500: interrupt-controller@1800000 {
        compatible = "arm,gic-v3";
...
        gic_its: msi-controller@1820000 {
            compatible = "arm,gic-v3-its";

Hi Bin,

For reference, I am using the device tree of the tqma62xx used by tq in their yocto build for linux kernel 6.1 (here: https://github.com/tq-systems/linux-tqmaxx/blob/kirkstone.TQMa62xx.BSP.SW.0001/arch/arm64/boot/dts/ti/k3-am62-main.dtsi#L17) Though I looked at 6.13-rc1 as well and this node is the same.

I was making reference to the fact that gicv3 only requires distribution and redistribution registers. So when using it as gicv3 only GICD and GICR are used. GICC/H/V are GiCv2 registers and are not needed by the gicv3 driver. So I was wondering if those GiCv2 registers are a leftover of a previous version or here for some sort of compatibility mode, in which case I would like to know if the repetition of the GICR line is intentional and if the addresses given for the gicv2 registers are correct.

Since I didn't find any reference to those GICC/H/V registers in the documentation I was a bit hesitant.

Hi Liu,

I did not know those register were required in the device tree, do you know where if and where I can find the value used in the documentation ? Or if they are filler used only for the device tree compatibility and do not reflect hw capabilities ?

Thanks again for your support

Hi SImon,

I am not a GIC expert, but I guess those values are in the ARM GIC manual.

The regions of GICC/H/V are mainly for emulating GICv2 in KVM, which are basically useless in Processor SDK. So we can consider they are devicetree fillers.

You might also notice a bug in the gic500 node in k3-am62-main.dtsi, that the second and third "reg" regions are duplicate of "GICR". It would causes kernel GIC driver to get wrong region data of GICC/H/V, but it won't cause any issue since GICv2 emulation is not used. I have reported the bug to our SW dev team, it should be fixed in future SDK.

Hi Bin,

The GiC addresses are specific to the SoC, ARM does not describe those. Do you know if anyone could confirm whether or not those registers (GiCC/H/V) are present in the hardware ? And if so at which addresses ?

Looking at device trees of other SoCs, some nodes have those registers and some do not, making me believe they are not as mandatory as the documentation suggests (and as you pointed out, the duplication of the redistributor would've made linux bug if it was used). However, when they are present the addresses used pass the sanity check of being 32 bits which is not the case in the dts I linked above (I thought cpu was 0x0 but I was mistaking and it is 0x100000000).

I only really need to know if those registers are present in the SoC or not, the discrepancy between the documentation (where they are not) and the device tree (where they are but the node is dubious) is what lead me to ask the question on this forum.

Thank you

Hi Simon,

Simon Plantier said:

I only really need to know if those registers are present in the SoC or not

It doesn't matter the registers present or not, the Linux kernel doesn't use them. The DT entries get passed into the GIC driver and assigned to variables, but the driver doesn't use these regions.

Hi Bin,

I don't need the information for linux but for an RTOS development. I used linux device tree because it is a BSP provided by the constructor and the difference with the documentation raised the question.

Thanks for your support.

Hi Simon,

In the first trial of research in our internal documentation, I am unable to find the memory map information of GICC/H/V.

Can you please help me understand why you would need the information for RTOS development? I thought you should only need GICD/R, but not GICC/H/V.

Hi Bin

We would like to know if using an application only compatible for gicv2 is possible on this SoC or if the gicv3 version is mandatory.

Hi Bin,

Thank you for your answers.