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AM6422: AM64x Sitara Processor: RESETSTATz warm state during supplies ramp-up

Lorenzo Rebonato
Prodigy 20 points
Part Number: AM6422

Tool/software:

Hello Support Team,

the switching characteristics of the AM64x RESETSTATz signal (Main Domain warm reset status, push-pull output) are explained in detail in the Processor Datasheet SPRSP56G,

however there is no mention about the RESETSTATz state during the power-on of the device. Even in the Technical Reference Manual SPRUIM2H I'm not able to find this information.

In another case, that of AM335x Sitara Processor and nRESETIN_OUT warm reset signal (input/output open drain), the Technical Reference Manual SPRUH73Q at par. 8.1.7.3.2 states that

"nRESETIN_OUT is not defined (can either be driven low or pulled up high) until all supplies are fully ramped
up. For nRESETIN_OUT to maintain a valid low state until the supples are ramped, an external buffer should be implemented, as shown in Figure 8-24."

Should I apply the same care also with the AM64x warm reset output and use an external buffer (for example, AUP buffer with 3-state output),

or is the valid low state of RESETSTATz guaranteed until the supples are fully ramped up?

Thank you in advance for your clarifications,

Kind Regards

Lorenzo

  • 0
    TI__Guru**** 158939 points

    Hello Lorenzo,

    Thank you for the query.

    Please refer to the pin attributes' table for the initial state of the pins.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 20 points

    Hello Sreenivasa,

    thanks for your reply. I went through the pin attributes table, but you will understand that double checking is necessary.

    Also for the AM335x nRESETIN_OUT signal the ball state at reset and reset relase is declared 0 in the pin attributes (datasheet SPRS717L, Table 4-2 here enclosed). Nevertheless this is not guaranteed and an external buffer is required to maintain a valid low state until all supplies are fully ramped up.

    The aim is to use the RESETSTATz output to keep in reset the periherals during the power-on sequence and until the Main warm reset is inactive (RESETSTATz high). Please confirm that we can rely on RESETSTATz for this purpose.

    Kind Regards,

    Lorenzo

  • 0 in reply to Lorenzo Rebonato
    TI__Guru**** 158939 points

    Hello Lorenzo

    Thank you.

    Lorenzo Rebonato said:
    The aim is to use the RESETSTATz output to keep in reset the periherals during the power-on sequence and until the Main warm reset is inactive (RESETSTATz high). Please confirm that we can rely on RESETSTATz for this purpose.

    Please refer to the SK schematics. We have the above use case implemented for many of the attached devices including memories.

    Regards,

    Sreenivasa