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Disabling Cache in a SharedRegion

Miguel Aguilar
Intellectual 855 points

Hi,

I'm working on a C6472 EVM and I would like to disable the cache for a shared region placed in the SL2 RAM, the idea is to share this region among the processor without the need of calling Cache_inv(), Cache_wb, etc, because I don't need the cache for my application, so I would like to improve the performance. I already tried this however it seems that what is being writen by one processor can not be read by the other processor.

Then my question is if by disabling the cache for a shared region means that the cache is skipped and all the data goes directly to the shared memory?

Thanks,

Miguel

  • 0
    TI__Mastermind 32475 points

    Miguel,

    The issue you could be running into is that SL2RAM is cached in the L1 caches (L1D and L1P).  You would need to make sure L1D is all SRAM also.  You could do this by setting L1D to "0K" cache. 

    Another option would be to put the shared region in external memory and make change the MAR bit for that particular region to be non-cacheable.

    I don't believe its possible to disable caching of SL2SRAM on evm6472 by way of MAR register bits.  FYI: On C66 devices, this is possible through way of the MPAX which allows you to remap the SL2SRAM to a different range of address.

    Judah