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AM6442: PCIe Clock Level not high enough. Internal resistors?

Michael Neumüller
Prodigy 56 points
Part Number: AM6442
Other Parts Discussed in Thread: CDCE6214

Tool/software:

Hi everyone

We are having technical issues with the AM6442 CPU. We use an external clockgenerator (CDCE6214) as the 100Mhz clock source for PCIe. Now we are assuming, that there is an internal pulldown resistor at the CPU side that is responsible for our problem. The clock provider is running in LP-HCSL mode and the wiring looks as follows:

According to the errata sheet https://www.ti.com/lit/er/sprz457h/sprz457h.pdf   the SERDES Output reference clock cannot be used (i2236).

Another reason is also i2241: PCIe: The SerDes PCIe Reference Clock Output can exceed the 5.0 GT/s Data Rate RMS jitter limit

Now according to our measurements and thoughts we are assuming, that there is an internal pulldown resistor that is responsible for our problem.

The voltage level is too low, not high enough according to the PCIe Standard (Voltage Cross).

Voltage Cross for PCIe Clock Signal:

Here the signals that we are measuring, we see that we end up with a cross voltage of 200mV:

.  

Is there any internal resistor, that can have influence at the CPU port W17 SERDES0_REFCLK0P and W18 SERDES0_REFCLK0P  ?

Can you confirm that there is an internal termination resistor, if so if it is possible to turn it off and what register write we have to do to turn it off?

  • 0
    TI__Intellectual 1385 points

    Hi Michael, 

    those amplitudes in waveform do look like you experience double termination.  Normally I believe that the LP-HCSL has internal 50ohm terminations.  I was unsure if you are showing in schematic the serdes soc clock inputs as having termination resistors to gnd, but if you did that is likely where double terminated with having the clock provider in LP-HCSL mode (50ohm internal).  There is not internal resistors of CPU port W17 or W18.  

    I do want to point out though that in the errata sheet, the 2 issues you mention are only issues with a Revision 1.0 of silicon.  Revision 2.0 of silicon will not have those issues.

    -James

  • 0
    Prodigy 56 points

    Hi James, there are not termination resistors on our SERDES SOC Clock Inputs. Are you sure about your statement about the missing internal resistors? In the errata sheet the i2306 it mentions internal termination. What is that about in the current silicon version 2? 

  • 0 in reply to Michael Neumüller
    TI__Intellectual 1385 points

    Hi Michael, yes I misspoke with saying there are not internal termination resistors.  If you were using PCIE as boot mode then SOC's ROM would have taken care of disabling the termination resistors for silicon revision 2.0 

    ? -> what software base are you using? (Linux etc) as I don't find a register in the TRM to point you and will need to bring in some s/w experts for additional help.  

    Is your application able to use with removal of the CDCE6214 as clock source, with silicon rev2.0 no longer affected by i2236 and i2241?

  • 0 in reply to James Pair
    Prodigy 26 points

    James, this issue is a duplicate as you may have guessed. I guess we can continue with only one of the issues.

    e2e.ti.com/.../

  • 0 in reply to Manuel Aebischer
    TI__Intellectual 1385 points

    Ok, I will close this and we can just use the : AM6422: Distorted Reference Clock on Serdes Refclock Input going forward.