J784S4XEVM: IPC RPMSG missing rpmsg-chrdev with custom memory layout

/*
 *  Copyright (c) Texas Instruments Incorporated 2021
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 *    notice, this list of conditions and the following disclaimer.
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 *    Redistributions in binary form must reproduce the above copyright
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
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 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/**
 *  \file c7x_mmu.c
 *
 *  \brief C7x MMU Config File
 */

#ifdef BUILD_C7X

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */


#if (defined (FREERTOS))
#include "Mmu.h"
#elif (defined (SAFERTOS))
#include "Mmu.h"
#endif
#include "memory_map_defines.inc"

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

#if defined(SOC_J721S2)
    #define MSMC_SIZE   0x00400000U /* 4MB */
#elif defined(SOC_J721E) || (SOC_J784S4)
    #define MSMC_SIZE   0x00800000U /* 8MB */
#endif

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

void IpcInitMmu(bool isSecure)
{
    Mmu_MapAttrs    attrs;

    Mmu_initMapAttrs(&attrs);

    if(true == isSecure)
    {
        attrs.ns = 0;
    }
    else
    {
        attrs.ns = 1;
    }

    /* Register region */
    attrs.attrIndx = Mmu_AttrIndx_MAIR0;
    (void)Mmu_map(0x00000000U, 0x00000000U, 0x20000000U, &attrs, isSecure);
    (void)Mmu_map(0x20000000U, 0x20000000U, 0x20000000U, &attrs, isSecure);
    (void)Mmu_map(0x40000000U, 0x40000000U, 0x20000000U, &attrs, isSecure);
    (void)Mmu_map(0x60000000U, 0x60000000U, 0x10000000U, &attrs, isSecure);
    (void)Mmu_map(0x78000000U, 0x78000000U, 0x08000000U, &attrs, isSecure); /* CLEC */

    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
    (void)Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, isSecure); /* DDR */
    (void)Mmu_map(0xA0000000U, 0xA0000000U, 0x60000000U, &attrs, isSecure); /* DDR */

    (void)Mmu_map(0x70000000U, 0x70000000U, MSMC_SIZE  , &attrs, isSecure); /* MSMC */
    (void)Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, isSecure); /* OCMC - 1MB */

    /* IPC VRing Buffer - uncached */
    attrs.attrIndx =  Mmu_AttrIndx_MAIR4;
#if defined(SOC_J784S4)
    (void)Mmu_map(SHARED_DDR_SPACE_START, SHARED_DDR_SPACE_START, 0x04000000U, &attrs, isSecure); /* VRING DDR */
#else
    (void)Mmu_map(SHARED_DDR_SPACE_START, SHARED_DDR_SPACE_START, 0x02000000U, &attrs, isSecure); /* VRING DDR */
#endif
#if defined(BUILD_C7X_1)
    (void)Mmu_map(C7x_1_IPC_DATA_BASE, C7x_1_IPC_DATA_BASE, 0x00100000U, &attrs, isSecure); /* C7X_1 DDR */
#elif defined(BUILD_C7X_2)
    (void)Mmu_map(C7x_2_IPC_DATA_BASE, C7x_2_IPC_DATA_BASE, 0x00100000U, &attrs, isSecure); /* C7X_2 DDR */
#elif defined(BUILD_C7X_3)
    (void)Mmu_map(C7x_3_IPC_DATA_BASE, C7x_3_IPC_DATA_BASE, 0x00100000U, &attrs, isSecure); /* C7X_3 DDR */
#elif defined(BUILD_C7X_4)
    (void)Mmu_map(C7x_4_IPC_DATA_BASE, C7x_4_IPC_DATA_BASE, 0x00100000U, &attrs, isSecure); /* C7X_4 DDR */
#endif

    return;
}

#endif /* #ifdef BUILD_C7X */