AM623: AM62x MPU compatibility support with QSPI Nand flash parts

Hi Srinivas,

Number 1 and 8 should be ruled out, because your requirement is a QSPI NAND Flash and not a OSPI NAND Flash.

Here is a description from TRM stating that for 1S-1S-4S operation, the ROM issues 0x6B command.

I have discussed this internally and got to know that if the flash parts requires any of the following two to be done:

1. CHECK A: If the flash part requires some additional commands to be send before ROM issues the 0x6B read command, then such flash is not supported.
2. CHECK B: If the flash part requires setting up of some additional registers before ROM issues the 0x6B read command, then such flash is not supported.

Now I have gone through the flash part's datasheet.

For the variants W25N02KWxxx I have not seen QE bit. Basically there is no QE bit, so CHECK B  is ruled out. We need to check for CHECK A.

For the variants W25N02JWxxx I have seen for ROM to issue 0x6B, the QE bit needs to be set to 1, so this falls under CHECK B, hence this flash should be ruled out as ROM does not support QE bit.

NOTE: This is an initial prompt response to take forward the discussions internally, and give you an idea as to what to look for when reading the datasheets.

I am attaching the datasheet which I referred:

W25N01JWxxx: https://www.winbond.com/resource-files/W25N01JWxxxGT_RevC_210524.pdf

W25N02KWxxx: https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25N02KW

Can you please attach the datasheet for W25N02JWxxx ?

We will be discussing this internally and fill the table after having another round of discussion with another expert.

Regards,

Vaibhav

Hello Srinivas

I made some minor updates to your post, as some of that was discussed was internal and not relevant for public domain. 

In general TI will not make any specific vendor recommendations. We have flash devices that are on the EVM and in case of QSPI we have done some internal testing replacing some of the OSPI NANDs with foot print compatible QSPI NANDs 

We can of course give some limited guidance if we know another customer has confirmed working , but that is a limited database. We have no plans to individually validate multiple vendors and multiple part # within a vendor space. 

However we will try to keep the customer educated on any constraints our ROM may present (which is what Vaibhav has posted) 

Additionally my understanding is that 

Since there is no JEDEC/xSPI/ONFI like standard for parallel NAND, so please also be cautious on features like continuous read and custom BBM, that some vendors offer but not supported by our xSPI IP. 

Please also make sure QSPI meets your boot time KPIs. 

Regards

Mukul 

Hi Vaibhav,

Thanks for your reply.

Attached is the requested datasheet of W25N02JWxxxx.

W25N02JWxxxFC_RevD_220921.pdf

Hi Srinivas,

Srinivas Tummalapalli said:

Attached is the requested datasheet of W25N02JWxxxx.

W25N02JWxxxFC_RevD_220921.pdf

I see that for this flash part as well, we have QE bite and this QE bit needs to be set to 1, in order to proceed with 1S-1S-4S.

Allow us time until next week, to comment on the tabular data which you put out here.

Thank you very much for your patience.

Regards,

Vaibhav

Hi Srinivas,

Allow me a day to comment on this, mostly the table should remain the same, but I am going to comment on the ROM constraints in detail and highlight what can be a workaround(if there is any). To get information on this, I am talking to the ROM team, and will update here once I collate everything.

Thank you very much for your patience.

Regards,

Vaibhav

Hi Srinivas,

Thanks for your patience.

The table will not change, but I am going to tell if you the ROM constraints.

Vaibhav Kumar said:

• CHECK A: If the flash part requires some additional commands to be send before ROM issues the 0x6B read command, then such flash is not supported.
• CHECK B: If the flash part requires setting up of some additional registers before ROM issues the 0x6B read command, then such flash is not supported.

These checks will still apply.

I checked with the ROM team, and got to know that there will be a Device Configuration table introduced which will have a field(16th bit) for Quad enable.

This can be set by the developer, based on the flash part requiring QE bit to be set for 1S-1S-4S transactions.

If this is taken care, then booting from 1S-1S-4S is possible.

NOTE: This is yet to come out and is in process of implementation. Currently I cannot provide a timeline for the release, but when I know one, I will update here on the thread.

Regards,

Vaibhav

Hi Vaibhav & TI Team,

A very Happy New Year 2025.

Thanks for your responses regarding this query.

Below is as per my understanding from your responses until now,

• W25N02KWxxx: Seems to be compatible with AM62x MPU but the constraint "CHECK A" is yet to be checked.
• W25N02JWxxx: Is ruled out due to the constraint "CHECK B" i.e Quad Enable bit (QE) pre-requisite has to be met which is not currently supported by TI AM62x MPU.  

Hence, I am planning to cross-check the constraint "CHECK A" for W25N02KWxxx with Winbond manufacturer (as "Check B" is not applicable for this flash part).

1. Can you please check and let me know whether AM62x MPU supports both the flash part variants i.e. W25N02KWxxIR (BUF = 1) & W25N02KWxxIU (BUF = 0)?

Regards,

Srinivas T

Hi Srinivas,

Srinivas Tummalapalli said:

A very Happy New Year 2025.

Happy New Year

Srinivas Tummalapalli said:

Can you please check and let me know whether AM62x MPU supports both the flash part variants i.e. W25N02KWxxIR (BUF = 1) & W25N02KWxxIU (BUF = 0)?

You are going to use a NAND flash part.

For a NAND Flash part we are currently not supporting sequential/continuous reads, only for NOR flashes sequential read is supported.

Srinivas Tummalapalli said:

Hence, I am planning to cross-check the constraint "CHECK A" for W25N02KWxxx with Winbond manufacture

Sure, thanks.

Regards,

Vaibhav

Thanks Vaibhav.

So, do you mean AM62x ROM supports Nand flash devices only in Buffer Read mode? (In Buffer read mode: the data output sequence will start from the Data Buffer location specified by the 16-bit Column Address and continue to the end of the Data Buffer).

Below is the snippet from W25N02KWxxxx_datasheet explaining Buffer Read mode (Section 8.2.17 Fast Read Quad Output (6Bh) at page # 46)

Best Regards,

Srinivas T

Hi Srinivas,

Thanks for your response.

Srinivas Tummalapalli said:

AM62x ROM supports Nand flash devices only in Buffer Read mode?

I will check with the ROM team and let you know if BUF = 0/1 is supported.

My answer to your question was from application point of view.

I have pinged the concerned ROM team and I will update you once I hear back from them.

Thanks for your patience.

Regards,

Vaibhav

Hi Vaibhav,

Good Day!

Further regarding the "CHECK A" constraint, below is the Winbond's response wrto QSPI Nand Flash P/N: W25N02KWxxIR(BUF=1 i.e. Buffer read mode). 

 " QSPI NAND device requires data to be loaded from a page (target page) to the buffer, so it requires 0x13 command and a page address before 0x6B read command ".

This seems to me like the "CHECK A" constraint is not met.

So, does this mean that this flash P/N: W25N02KWxxIR (BUF=1 i.e. Buffer read mode) is not supported by AM62x MPU ?

Regards,

Srinivas T

Hi Srinivas,

Thanks for your response.

I have talked with the ROM team, and here is the input I got.

ROM supports only one mode, that is, Buffer Read Mode. So BUF=1 in this case.

ROM checks the default mode for Winbond. If BUF=0 by default, then ROM changes it to BUF=1.

Regards,

Vaibhav

Thanks Vaibhav.

Can you please also reply for the shared update wrto "CHECK A" constraint of AM62x RoM ?

i.e.

Below is the Winbond's response wrto QSPI Nand Flash P/N: W25N02KWxxIR(BUF=1 i.e. Buffer read mode). 

 " QSPI NAND device requires data to be loaded from a page (target page) to the buffer, so it requires 0x13 command and a page address before 0x6B read command ".

This seems to me like the "CHECK A" constraint of AM62x MPU is not met?

Does this mean that this flash P/N: W25N02KWxxIR (BUF=1 i.e. Buffer read mode) is not supported by AM62x MPU ?

Regards,

Srinivas

Hi Srinivas,

I had a word with Shashank as well and he asked me few questions as well.

So addressing it all together here.

So the read operation is not dependent on a particular SoC, but it depends on the flash part which is being used.

For a NOR Flash, continuous reads happen and for NAND flash page reads happen(which is not sequential).

Srinivas Tummalapalli said:

This seems to me like the "CHECK A" constraint of AM62x MPU is not met?

Current state of ROM is that the check A is not met. I can comment on the timeline for the implementation of ROM setting QE bit for flash parts like Winbond.

I have asked ROM team for the timeline and would comment on the same once I hear back from them.

Regards,

Vaibhav