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AM6442: Configuring AM6442 PRU GPIO Pin as Output and Input Simultaneously

Shivangi Jain
Prodigy 70 points
Part Number: AM6442

Tool/software:

Hello TI Community,

I am working on a project using the AM6442 processor, and I need some guidance regarding the GPIO pin configuration. Specifically, I want to configure a GPIO pin as a General Purpose Output (GPO) controlled by the PRU firmware, while also using the same GPIO pin as an input on the A53 core for generating an interrupt.

My question is: Is it possible to configure the same GPIO pin as both an output in PRU firmware and an input for the A53 core simultaneously? If so, could you provide any advice on how to achieve this setup?


Thank you in advance for your help!

  • 0
    Prodigy 70 points

    Hi TI Team,

    I wanted to follow up on my previous query regarding GPIO configuration on the AM6442 processor.

    To reiterate, I am looking to configure a GPIO pin as both an output (controlled by the PRU firmware) and an input (to generate an interrupt for the A53 core). If this setup is not feasible, I plan to use a GPIO pair where one serves as the input for the A53 core and the other as the output for the PRU core.

    Could you please advise on this or provide any recommendations? 

    Thanks,
    Shivangi

  • +1
    TI__Guru** 100750 points

    Hello Shivangi,

    Summary: not supported

    Short answer: What you are trying to do is not supported in hardware, if you want to configure the pin to be a PRU GPO, and the GPIO input, at the same time.

    More details 

    AM64x has a bunch of different groups of circuits inside of it that are clustered into separate peripherals (e.g., the PRU subsystem, and the GPIO modules, are two different groups of circuits).

    Each of these peripherals has a bunch of signals coming in and out of the peripheral.

    We have many more input and output signals than physical pins on the bottom of the processor. So how do we make it work?

    We route signals from several different peripherals to the same hardware pin. Then we use the pinmux settings to select which of those internal signals gets muxed to the hardware pin. These hardware muxes only allow a single signal to be connected to the hardware pin at once.

    Thus, you can route a PRU GPO signal to one specific pin, OR you can route a GPIO signal to that specific pin. However, you cannot route both at the same time.

    What are other options? 

    If you are not actually limited by the processor pins, and you just want the PRU to be able to write to a trace on your board, and the A53 core to be able to read from that same trace, then I would suggest setting your pinmux so that the GPIO signal went to one hardware pin, and the PRU GPO signal went to another hardware pin. Then you could simply connect both pins to the same trace on your board.

    Regards,

    Nick

  • 0
    TI__Mastermind 47561 points
    Shivangi Jain said:
    Specifically, I want to configure a GPIO pin as a General Purpose Output (GPO) controlled by the PRU firmware, while also using the same GPIO pin as an input on the A53 core for generating an interrupt.

    This can be achieved via generating software interrupt using ICSSG INTC (using R31 event interface). Total latency will be bounded under 1 clock cycle from PRU side

    ldi R30.w0, 1

    ldi R31.b0, 32+event_num ;setup event_num to channel to host mapping in ICSS INTC as a pre-requisite

  • 0 in reply to PratheeshGangadhar
    TI__Guru** 100750 points

    Edited Jan 9 2025

    You described this valid path:
    external signal --> pin --> PRU GPI --> generate interrupt from PRU's INTC to Linux A53

    PRU GPI: disabled
    PRU GPO:
    PRU GPO --> pin --> outside of processor
                  |----> generate interrupt from PRU's INTC to Linux A53

    However, I assumed that we cannot have both a PRU GPI and a PRU GPO signal connected to the same processor pin simultaneously. Is that assumption correct? If so, do you see people working around that limitation by modifying the pinmux settings in real time to flip between PRU GPI and PRU GPO?

    I figured that manually changing the pinmux settings during runtime would be nondeterministic, both from the writes between the PRU core and the control module registers, and from the standpoint of how long it would take for the register settings to get applied.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Guru** 100750 points

    Hello Shivangi,

    Where are you expecting the interrupt to Linux to come from?

    Did you want the PRU GPO to be able to write to the processor pin, and also send an interrupt to Linux A53?

    Or did you want the Linux interrupt to come from an external signal from outside of the processor?

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Guru** 100750 points

    Edited my previous response, as indicated in RED