AM335x Pinmux

Hi!

I'm working on a very similar design. The biggest difference is that I just need 1 x CAN and 2 x SD and was planning to use NAND Flash. The problem is, some NAND Flash pins are taken by the other RMII interface. I'll figure it out somehow and in the extreme case will use an SD slot instead.

I think your pin mapping is OK but a TI expert would have to confirm. I can confirm that RMII PHYs are supported in Linux. That is actually a very common practice.

Thanks for the reply Risto,

Yes, I'm not using Flash for the same reason. This seems to be a very powerful device but insufficient pins to take full advantage of it! Oh well...

Hi Risto

Using 2xEth (RMII) and a multiplexed bus for GPMC (for instance, IO Set 49 and 46 in GPMC setup) didn´t solve your problem ?

Marcelo

Yes, I think I got it sorted out pretty well by using 2xRMII. I have the required GPMC pins available for 8-bit NAND flash and even some address pins for interfacing an external UART (I need 8 UARTs).

***Risto***

I've got a similar problem. I try to find a configuration that supports both RGMII ports together with both McASP ports running in synchronous mode (common clock for transmit and receive) while having all 8 serial data lines of the McASP blocks available. There would actually be pin combinations which make all needed signals available, but so far I've always got an IO Set Violation warning flagged up.

Have I missed something or is there really no way to achieve this?

Cheers

Stefan

Many of the AM335x peripheral inputs and output signals were multiplexed to more than one device terminal as a way to reduce the limitations of pin-multiplexing. Multiplexing signals to multiple terminals adds a significant design complexity because each signal path needs to be properly timed with all other signals of the associated peripheral interface. If several signals of a peripheral interface can be multiplexed to multiple terminals, the number of possible combinations can be large. This makes it prohibitive to close timing on all possible combinations. Therefore, the AM335x does not support all possible combinations of pin-multiplexing. The supported combinations of pin-multiplexing for a specific peripheral interface are referred to as valid IO Sets.

Texas Instruments has developed a Windows application called Pin Mux Utility that helps a system designer select the appropriate pin-multiplexing configuration for their AM335x based product design. This tool provides a way to select valid IO Sets of specific peripheral interfaces to insure the pin-multiplexing configuration selected for a design only uses valid IO Sets supported by AM335x.

The Pin Mux Utility is the best way to determine if your application can be implemented with valid IO Sets. AM335x devices do not support pin mux configurations that do not use valid IO Sets.

Regards,

Paul

Thanks Paul,

I did use the Pin Mux Utility, that's how I found the IO Set Violations. I also had the impression it might be the testing that was at the basis of the IO Sets. So thanks for confirming I was on the right track.

But that leaves me with the impression that the combinations not officially supported as an IO Set may well still work, only that there's no guarantee. The IO Set violation could be regarded as a "do this at your own risk" warning rather than a "this won't work" warning. Is that what you are saying?

What governs the inclusion of a particular mux combination into an official IO Set? I would guess it is a particular use case that is giving rise to a particular IO Set. In my case, that would mean that having both GBit ethernet ports active and still using all serial audio ports was not regarded as an important use case, although there would be several different mux combinations that could achieve it. Is there a way to promote the importance of such a use case, so that it becomes officially supported (I guess the answer involves money)?

But maybe I can still somehow find a valid combination through the Pin Mux Utility. I haven't yet got the hang of it enough to be sure I've exhausted my options.

Cheers
Stefan

Hi Stefan

> But that leaves me with the impression that the combinations not officially supported as an IO Set may well still work, only that there's no guarantee.

Yes, I had the same impression. In my case, using two RMII and the external (multiplexed) 16 bits bus, it was necessary to leave GPMC_WAIT0 and GPMC_WPN (write protection pin) since they are used by RMII. This action generated a yellow box (IO Subset). 

In such situation, I am considering that we can use only one WAIT (GPMC_WAIT1) in my design (I do not have interleaved flash memories, for instance) and it is possible to create a GPMC_WPN by GPIO. However, this is based on my interpretation of the manual and I would like to see this scenario officially supported in pinmux. Some warning or workarounds provided by pinxmux would be welcome in such case, giving hints to the user.

Marcelo Barros

Hi all,

The same way Marcelo reported, we are trying to get two ethernet both in traditional MII interface with AM335X.

In the previous posts the predefined IO Sets are mentioned as the valid IO Sets, and this let me unsure about what can I do.

We have tried all the predefined IO Sets, but none of them comes with all the signals we expect. Tipically is always missing the CRS_DV, RX_ER, COL and REF_CLK. And sometimes we have also some signals conflicting which require some approach.

Questions are:

1) can we manually choose/deselect the missing/conflicting signals in other columns/modes by right-clicking "Change Selected Mux Mode Cells" ?

2) Is there any impact, risk or care to be taken in software with these manual choices?

Many thanks,

Rodrigo Mendes