AM6421: OSPI frame is split？

Hi Vaibhav,

I'm not operating NOR flash.

The scenario is to use OSPI and FPGA for communication. 

I just want to know if this kind of frame-splitting scene is as expected.

BR

Ryan

Hi Ryan,

Ryan LIU said:

I'm not operating NOR flash.

Okay I understood.

The write operation happens in some chunks of memory sizes, so maybe that is why you are seeing frame splitting.

Can you please attach a more clarifying diagram? I cannot understand what is clock/data lines/chip select line.

Regards,

Vaibhav

Hi Vaibhav,

The write operation starts at address 0x00 with a quantity of 0x40.

On the waveform, it is observed to be split into three frames, in sequence:

The first frame starts at address 0x10 with a quantity of 0x20.

The second frame starts at address 0x00 with a quantity of 0x10.

The third frame starts at address 0x30 with a quantity of 0x10.

Other observations，address 0x10 is written before 0x00.

BR

Ryan

Hi Ryan,

Ryan LIU said:

with a quantity of 0x40

What do you mean by quantity here?

Regards,

Vaibhav

Hi Vaibhav,

When writing data, you need to have a starting address and size, which may be described here as a more appropriate size。

BR

Ryan

Hi Ryan,

So just to confirm.

Ryan LIU said:

The write operation starts at address 0x00 with a quantity of 0x40.

This is like entire frame starting at address 0x0 and 64 bytes being transferred?

Ryan LIU said:

The third frame starts at address 0x30 with a quantity of 0x10.

And last frame starting at address 0x30 and sending 16 bytes of data?

Can you tell me more about what this address here is?

When you say that the entire frame starts at address 0x0, does this means that you are writing to the flash at offset 0x0?

Please clarify my understandings.

Regards,

Vaibhav

Hi Vaibhav,

Yes, address is mean that offset.

BR

Ryan

Hi Ryan,

Ryan LIU said:

Yes, address is mean that offset.

Okay I got it. 

I will check the diagrams which you have attached, and I am assuming that you initiated the transfer write direct just once with address/flash offset as 0x0 and size as 64 bytes, but then you saw 3 frames being sent out instead of just one big frame consisting of 64 bytes.

Moreover, is your SBL Null/Bootloader image flashed at offset 0x0 in the flash? If that is the case, it is recommended to not write any value to 0x0 offset as it will overwrite your SBL Null flashed image.

Regards,

Vaibhav

Hi Vaibhav,

“I will check the diagrams which you have attached, and I am assuming that you initiated the transfer write direct just once with address/flash offset as 0x0 and size as 64 bytes, but then you saw 3 frames being sent out instead of just one big frame consisting of 64 bytes.”，Yes, that's the case.

Also, thank you for the reminder, this is another device on the bus operation, with a different CS, and the NOR flash will not respond.

BR

Ryan