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AISGen won't allow PLL1 setting used by GEL file?

MikeH
Guru 15580 points
Other Parts Discussed in Thread: OMAP-L138

I am (once again) having trouble debugging my OMAP-L138 boot up problems. My AIS generated .bin file contains both ARM and DSP code. Both load and run in DDR. During debugging I use a Logic PD GEL file that sets the DDR PLL1 with the following values.

Set_DDRPLL_150MHz() {

    device_PLL1(24,1,0,1,2);

    GEL_TextOut("\tPLL1 init done for DDR:150MHz\n","Output",1,1,1);

These values allow me to successfully load and run both the ARM debugging code and the DSP debugging code into DDR memory. However, when I attempt to use the above values in AISGen I get an error when setting PLL1 DIV1 to zero (it is looking for a value between 1 and 32). Therefore I am unable to program the AIS generated file with the same PLL1 values as I use for debugging. 

I am not sure the DDR PLL is the issue with booting, but I am trying to eliminate it as a potential problem. Any suggestions?

 

  • 0
    TI__Expert 8890 points

    Mike,

    The PLL divisor and multiplier values in AISgen are the "real" divisor values, not the "off by one" values that you would program directly into the registers (as in the GEL file).  Thus, setting the DIV1 parameter to 1 will program a 0 to the register during boot.  The read-only text boxes on the PLL0/1 tabs show you the actual clock speeds (in MHz) that you will achieve at run time.  One thing to note is that the listed DDR clock is the "2x" value, not the clock output by the DDR module.

    Hope this helps.  Please let me know if you have any additional questions about AISgen.

  • 0 in reply to Joe Coombs
    Guru 15580 points

    Thanks Joe. I am now using AISgen to calculate custom clock speeds. Handy!