PROCESSOR-SDK-J784S4: mcusw build issue

Hello,

Please follow the URL to build mcusw examples

Regards

Tarun Mukesh

How to convert can_profile_app_freertos_mcu1_0_release.xer5f to .elf or .bin ?

I would like to load the app from debugger and step the code.

In the SDK., can we build app in the format that can load and run from debugger ? if yes, how to build app that way ?

Hello,

Can_profile_app_freertos_mcu1_0_release.xer5f is itself an .elf file renamed as .xer5f -> r5f represents the core of the executable.

In the same URL pasted above, there are steps to load from CCS debugger.

Jim Zhang said:

In the SDK., can we build app in the format that can load and run from debugger ? if yes, how to build app that way ?

PLease go through the link pasted above all the steps are mentioned.

Regards

Tarun Mukesh

I went through the link, it does not have the answer I need.

You are hired to just tell me to look your vague instruction or poor document ?  If I can find the answer there, I will not ask you here.

The E2E responses will be delayed due to the TI Holiday (Christmas). Thank you for your patience.

Hello,

Jim Zhang said:

How to convert can_profile_app_freertos_mcu1_0_release.xer5f to .elf or .bin ?

I would like to load the app from debugger and step the code.

In the SDK., can we build app in the format that can load and run from debugger ? if yes, how to build app that way ?

I answered you query very specifically.

Tarun Mukesh Puvvada said:

Can_profile_app_freertos_mcu1_0_release.xer5f is itself an .elf file renamed as .xer5f -> r5f represents the core of the executable.

This itself is the executable file which you can load via CCS debugger. The steps to build and load the app are specifically mentioned in the document.

With steps listed at (Setup Build Environment) completed MCAL m

Modules can be built

1. Go to folder ($SDK_INSTALL_PATH)/mcusw/build

J721E

1. Can Profiling Application
   • make -s can_profile_app BOARD=j721e_evm SOC=j721e BUILD_PROFILE=release CORE=mcu1_0 BUILD_OS_TYPE=freertos
   • make -s can_profile_app BOARD=j721e_evm SOC=j721e BUILD_PROFILE=release CORE=mcu2_1 BUILD_OS_TYPE=freertos

• On Successful compilation, binary folder would be created in ($SDK_INSTALL_PATH)/mcusw/binary/(driver name)_app/bin/j721e_evm

Jacinto Family of Devices

1. Ensure boot mode of the EVM is configured as described in (J721E/J7200/J721S2 EVM NO Boot Mode / CCS)
2. UART / Console for demo application logs / messages
   • J721E EVM had 2 UART ports
   • UART port named MCU UART would be used when demo applications are hosted on MCU R5F (mcu 1 0)
   • UART port named Main UART would be used when demo applications are hosted on MAIN R5F (mcu 2 1)
   • Refer EVM Image at (J721E EVM)
3. CCS Setup & Steps to run from CCS Refer the SDK Release Notes user guide for generic test setup details and steps to run the examples/demos using CCS/SBL.
4. Reset MCU_Cortex_R5_0_0 core
5. In core MCU_Cortex_R5_0_0, load binary (driver name)_app_mcu1_0_(release or debug).xer5f
   • J721E MCAL Binaries is available at ($SDK_INSTALL_PATH)/mcusw/binary/(driver name)_app/bin/j721e_evm/
   • Some of the example applications (ipc) would have more than 1 binaries. The name of the binaries specify the core that it's intended to hosted on
6. Run example
   • Expect to see prints on CCS console or UART console (Setup Build Environment)
   • To run demo applications, please refer individual application notes (MCU Demos)
7. On Core MCU 2 1
   • UART port on which prints are displayed is different, ensure to connect UART port named UART on the EVM
   • J721E MCAL Binaries is available at ($SDK_INSTALL_PATH)/mcusw/binary/(driver name)_app/bin/j721e_evm/(driver name)_app_mcu2_1_(release or debug).xer5f
   • Connect to MAIN_Cortex_R5_0_1
   • Load binaries and run
   • To run demo applications, please refer individual application notes (MCU Demos)

The steps are similar to J784S4 as well except board ,soc and core specific details.

Regards

Tarun Mukesh

I built gpt_app and load it with lauterbach: ti_sdk/mcusw/binary/gpt_app/bin/j784s4_evm/gpt_app_mcu1_0_release.xer5f

I did not get any symbol for the binary. It looks like the code is not loaded to DDR

any scripts to load the exe to DDR usingTrace32?

Another question is about the core naming convention. It is related to app the link file. What type core are those mcu 2 0 /mcu2 1 ? It just tell 1ST MCU core 0/1ST MCU core 1. 

Hello ,

Jim Zhang said:

any scripts to load the exe to DDR usingTrace32?

Yes we have cmm scripts to load for using Trace 32 but please raise another query since it deviates from build issue.

Jim Zhang said:

Another question is about the core naming convention. It is related to app the link file. What type core are those mcu 2 0 /mcu2 1 ? It just tell 1ST MCU core 0/1ST MCU core 1. 

MCU1_0 and MCU1_1 are MCU domain cores whereas MCU2_0 ,MCU2_1,MCU3_0,MCU3_1 etc... are main domain cores.Based on your requirement you need to build the respective core binaries.

Regards

Tarun Mukesh

My question is MCU2_0 ,MCU2_1,MCU3_0,MCU3_1 are R5F cores ? or 
C7x cores ?