C6748 EDMA - DMAQNUM and DRAE?

Robert56682 said:

For DRAE, some example code I have uses region 1 for EDMA, which I've designed in as below, for the McASP transmit and receive:

    for Tx, CSL_FINST( EDMA3->DRA[ 1 ].DRAE, EDMA3CC_DRAE_E1, ENABLE );

    for Rx, CSL_FINST( EDMA3->DRA[ 1 ].DRAE, EDMA3CC_DRAE_E0, ENABLE );

Does that seem right, and why region 1, instead of the DMA Region Access Enable Registers for region 0, 2 or 3?

Here's a snippet from the data sheet:

The only EDMA interrupt physically connected to the DSP is the Region 1 interrupt.  Therefore you must use Shadow Region 1 for generating DSP interrupts.  Similarly you must use Shadow Region 0 to generate an ARM interrupt, since only the Region 0 interrupt is physically connected to the ARM.

Robert56682 said:

For DMAQNUM, once again example code showed DMAQNUM0 being used, and Q0 for it.  But why not DMAQNUM 0, 2 or 3?  Also, for the DMAQNUM, can I use Q0 for the transmit to McASP and Q1 for receiving from it, like below?

    for Tx, CSL_FINST( EDMA3->DMAQNUM[ 1 ], EDMA3CC_DMAQNUM_E1, Q0 );

   for Rx, CSL_FINST( EDMA3->DMAQNUM[ 1 ], EDMA3CC_DMAQNUM_E0, Q1 );

This one might change depending on your system.  You should put shorter higher priority transfers in one queue while putting the longer lower priority transfers in a different queue.  That will allow the short transfer to take priority over the long transfer to help you better manage real time deadlines.

Brad Griffis said:

The only EDMA interrupt physically connected to the DSP is the Region 1 interrupt.  Therefore you must use Shadow Region 1 for generating DSP interrupts.  Similarly you must use Shadow Region 0 to generate an ARM interrupt, since only the Region 0 interrupt is physically connected to the ARM.

Thanks Brad.  I missed that in the data sheet!

Brad Griffis said:

This one might change depending on your system.  You should put shorter higher priority transfers in one queue while putting the longer lower priority transfers in a different queue.  That will allow the short transfer to take priority over the long transfer to help you better manage real time deadlines.

Is it true that Q0 is higher priority than Q1?  The EDMA I'm working on is to service real-time data from the McASP, where both Rx and Tx are high priority.  So you don't see an issue with putting both in Q0 (if it's highest priority)?

Robert