PCIe Root Complex gen2 operation on DM8168EVM.

RY9983 said:

I have set LINK_CTRL2.TGT_SPEED as gen1 or gen2, other register settings are the same value.

Can I confirm about below?

- What should I do to prevent "Bad DLLP" and "Receiver Error"?

When do you set the target speed? After first having link established or even before initiating link training?

RY9983 said:

 - Can PCIe RC operate as PCIe gen2 on DM8168EVM?

Yes. When you are setting target speed as GEN2 and the peer has GEN2 capability, the link re-training should lead to a GEN2 link.

   Hemant

Hello Hemant,

Thank you very much for your advice.
I would like to send feedback about your questions.

HemantPedanekar said:

When do you set the target speed? After first having link established or even before initiating link training?

 

I set LINK_CTRL2.TGT_SPEED as gen2 after link established and before initiating link.
But, "Bad DLLP" and "Receiver Error" have been occured on both of them.

I would like to send you additional information.
I have be aware of the problem under following condition as Root complex gen2 operation.

 - As one of all case : "Bad DLLP" and "Receiver Error" have been occured before access to endpoint device.
 - As one of all case : "Bad DLLP" and "Receiver Error" have been occured after correctly access to endpoint device.
 - "Bad DLLP" and "Receiver Error" have been occured within 1 minute.
 - DEBUG0.LTSSM_STATE is always 11h even when "Bad DLLP" and "Receiver Error" occur. (link have not been disconnected.)

To prevent errors, do you have any idea?

One of my question mark is..
 - By environmental impact, do the "Bad DLLP" and "Receiver Error" often occur, even if I set up PCIe correctly?

Best regards,
RY

These errors are detected at physical layer level, eg., due to CRC errors and generally are correctable by retransmission etc. I guess normally such error should not be there and perhaps indicate some issue at link level.

One option is to verify signal levels etc on the PCIe lines and see any h/w issues. Otherwise you can hookup  a PCIe analyzer and check what exactly is happening at DLLP level.

   Hemant

Hemant,

Thank you very much for your support.
I have found the problem which is  a mistake on interrupt routine.
I can operate PCIe as gen2 Root Complex mode now.

Your advice is helpfull for me to finding the problem.
Thank you again.

Best regards,
RY