Tool/software:
Dear supporter,
I'm trying to run C7x hello world Freertos example on MCU SDK 10 using L2SRAM. The default linker routes all section to DDR, I need the stack and heap route to L2SRAM. But I can only point the .sysmem to SRAM. Whenever I point the .stack to SRAM, the debugger cannot jump to main function. Could you please help me change the linker to make hello world Freertos project run on SRAM?
Thank you very much!
Hi Jack,
Thanks for your patience.
Can you please try with the below linker.cmd file?
--ram_model
-heap 0x20000
-stack 0x20000
--args 0x1000
--diag_suppress=10068 /* to suppress no matching section error */
--cinit_compression=off
-e _c_int00_secure
#define DDR0_ALLOCATED_START 0x80000000
#define C7X_ALLOCATED_START DDR0_ALLOCATED_START + 0x19800000
#define C7X_RESOURCE_TABLE_BASE (C7X_ALLOCATED_START + 0x00100000)
#define C7X_BOOT_BASE (C7X_ALLOCATED_START + 0x00200000)
#define C7X_VECTOR_BASE (C7X_ALLOCATED_START + 0x00400000)
#define C7X_DDR_SPACE_BASE (C7X_ALLOCATED_START + 0x00410000)
MEMORY
{
L2SRAM (RWX): org = 0x7E000000, len = 0x00100000
DDR0_RESERVED: org = 0x80000000, len = 0x19800000 /* Reserved for A53 OS */
C7X_IPC_D: org = C7X_ALLOCATED_START, len = 0x00100000 /* 1MB DDR */
C7X_BOOT_D: org = C7X_BOOT_BASE, len = 0x400 /* 1024B DDR */
C7X_VECS_D: org = C7X_VECTOR_BASE, len = 0x4000 /* 16KB DDR */
C7X_CIO_MEM: org = C7X_DDR_SPACE_BASE, len = 0x1000 /* 4KB DDR */
C7X_DDR_SPACE: org = C7X_DDR_SPACE_BASE+0x1000, len = 0x01BF0000-0x1000 /* 27.9MB - 4KB DDR */
}
SECTIONS
{
boot:
{
boot.*<boot.oe71>(.text)
} load > C7X_BOOT_D ALIGN(0x200000)
.vecs > C7X_VECS_D ALIGN(0x400000)
.secure_vecs > C7X_DDR_SPACE ALIGN(0x200000)
.text:_c_int00_secure > C7X_DDR_SPACE ALIGN(0x200000)
.text > C7X_DDR_SPACE ALIGN(0x200000)
.bss > C7X_DDR_SPACE /* Zero-initialized data */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.data > C7X_DDR_SPACE /* Initialized data */
.cinit > C7X_DDR_SPACE /* could be part of const */
.init_array > C7X_DDR_SPACE /* C++ initializations */
.stack > L2SRAM
.args > C7X_DDR_SPACE
.cio > C7X_CIO_MEM
.const > C7X_DDR_SPACE
.switch > C7X_DDR_SPACE /* For exception handling. */
.sysmem > L2SRAM /* heap */
GROUP: > C7X_DDR_SPACE
{
.data.Mmu_tableArray : type=NOINIT
.data.Mmu_tableArraySlot : type=NOINIT
.data.Mmu_level1Table : type=NOINIT
.data.gMmu_tableArray_NS : type=NOINIT
.data.Mmu_tableArraySlot_NS : type=NOINIT
.data.Mmu_level1Table_NS : type=NOINIT
}
.benchmark_buffer: > C7X_DDR_SPACE ALIGN (32)
}
Also add the MPU region entry for L2SRAM memory region. Please refer below screenshot.
Please let us know if the above solution works.
Regards,
Tushar
Dear Tushar Thakur,
Thank you for your support, I can run with this linker and MMU setup. But there is a strange when I want to confirm if it is really run on L2SRAM. I wrote a small test to see if the pointer address is really on SRAM, and local variable is on stack (SRAM). But when I leave the optimization off, I saw pointer address is located on DDR. And when I change optimization level to 0 or 1, I saw it on SRAM.
Why optimization off leave the pointer on DDR even linker set .sysmem on L2?
Opt- off
Opt-1
Thank you for your support,
Jack
Hi Jack,
It seems that the value shown in the expression/variable view of CCS are not accurate or not reflecting the exact state.
Can you please try printing the address value? I am able to see that the variables are located at L2SRAM even when optimization are off.
Please refer below image.
Regards,
Tushar