[FAQ] AM644x / AM642x / AM641x / AM243x (ALV) Design Recommendations / Custom board hardware design – common queries for PMIC TPS65219 and TPS65220

HI Board designers,

Refer below, common E2E queries and replies for TPS65219

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1339010/tps65220-pmic-features-understanding?tisearch=e2e-sitesearch&keymatch=tps65220#

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1329416/tps65220-request-a-tps65220-circuit-review-and-related-inquiries-request-a-review?tisearch=e2e-sitesearch&keymatch=tps65220#

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1308575/faq-tps65220-tps6522053rhbr-schematic-review-for-am64x/4979020#4979020

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1290837/tps65220-tps6522053rhbr?tisearch=e2e-sitesearch&keymatch=tps65220#

 Please find the responses below and let us know if you have any questions.

• The VSEL_SD/VSEL_DDR pin is configured to set the output voltage on LDO1 which is a free 400mA power resource. If customer is not using LDO1, then they can connect the VSEL_SD pin to ground with a pull-down resistor. Here is the configured polarity of the VSEL_SD pin:
  
  • If VSEL_SD is HIGH (pull-up to the output of the 3.3V load switch), LDO1 = 3.3V (requires 3.3V on PVIN_LDO1)
  • If VSEL_SD is LOW (pull-down to GND), LDO1 = 1.8V
• The nRSTOUT pin is used to drive the MCU_PORz in the recommended PDN. The MCU_PORz on the processor side has a 1.8V domain. If nRSTOUT is directly connected to MCU_PORz, it will need a pull-up to a 1.8V supply (i.e. Buck2). If customer has a buffer, AND gate or any other logic circuitry between nRSTOUT and MCU_PORz, then the pull-up on the PMIC side can be either 1.8V or 3.3V (output of 3.3V load switch).

Regards,

Sreenivasa

Hi Board designers

Input regarding selection of PMIC:

The recommend PMIC(s) on the product folder or used on the SK or EVM schematics has been designed considering the power sequencing, supply rail output slew, nRSTOUT (reset output) delay output from PMIC connected to MCU_PORz after all the supplies ramp for clock to be stable and the sizing of the supply rails based on the processor worst case current draw.

When choosing an alternate non-TI PMIC, the recommendation for custom board designers is to review the relevant collaterals including the data sheet and Maximum Current Ratings document and follow the requirements/recommendations. The recommendation is to review the slew rate requirements, Power-up and power-down sequence sections of the data sheet and confirm the non-TI PMIC based power architecture follows the recommendation.

An important point to note is the processor does not support dynamic scaling of the core voltage or the analog supplies.

Inputs regarding supply decay

Refer below FAQ

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1485094/faq-am62a7-power-rails-decay-note-in-latest-datasheet/5703704#5703704

I have placed the note in both sections because it applies to both power-up and power-down. The power-up sequence should not begin until all power rails are below 300mV, and the power-down sequence is not complete until all power rails are below 300mV.

Regards,

Sreenivasa

HI Board designers, 

Inputs on power supply sizing:

Using Maximum Current Ratings application note vs Power Estimation Tool PET 

The max current app note is representing the current draw for a group of rails. Please note that it is not expected for this current to necessarily be replicated in the power estimation tool. The PET will tend to show more average use case power while the max current app note is intended to be used for power supply sizing as it will allow for the max transient on these groups with some margin. The PET should not be used for power supply sizing.

Regards,

Sreenivasa

HI Board designers, 

Note:

How were these pdn specs derived? Is it based on worst case analysis?

Yes it is based on worst case load transient estimates for a given SoC design.

The Target impedance for AM62x and AM62xSiP will be identical as the same worst case load transients exist on both designs since they share the same die.

Via sharing recommendations in the escape application note are only made to help guide a customer to escape the design with fewer vias in the VCA regions. The number of vias used for escaping signals will ultimately depend on the specific customer use-case, the number of interfaces that need to be implemented and the layer count. If the specific use case allows the customer to use more vias for VDD_CORE in the VCA regions, that is definitely a valid approach. Per-pin loop inductance guidelines are more applicable for single-pin supplies that are connected to a decap. In case of multi-pin supplies like VDD_CORE where there are a number of parallel connections to multiple pins/decap thru multiple vias, it is hard to tie it back in to a per-pin requirement. The most important target to meet is the impedance target specified in Table 7-6 of the PDN Applications note. This table is the same for AM62x and AM62x SiP.

We do not include Buck output inductance in PDN simulations.

For VDDS_DDR: we do not recommend using target impedance as the signoff for DDR.
Refer to the AM62x, AM62Lx DDR Board Design and Layout Guidelines which outlines all details of power aware SI/PI simulations
that need to be run. The eye mask checks from these power aware simulations are the signoff.

Power Distribution Networks: Implementation and Analysis

Sitara Processor Power Distribution Networks: Implementation and Analysis

https://www.ti.com/lit/pdf/sprac76

Note: The decoupling capacitor numbers and type on the SK/EVM are only intended to serve as a guideline for customers. The true pass/fail criteria is the target impedance published in the PDN app note.

High Speed Board design and Signal integrity simulation 

https://www.ti.com/lit/pdf/spraar7

https://www.ti.com/lit/pdf/spracn9

https://www.ti.com/lit/pdf/sprabi1

We are using AM6442BSDGHAALV in one of our design and we are calculating the ZTarget for VDD_CORE using the below formula

Ztarget = (Voltage Rail x %Ripple) / 0.5 x Imax

                   Voltage Rail = 0.75V

                   %Ripple = 1.6%

                   Imax = 2A

        %Ripple = 1.6% had arrived based on the below methodology.

1) We are using the PMIC: TPS6522053RHBR whose BUCK-1 Minimum output voltage is 0.73875V (0.75V Typical). Considering the ripple of -1.5% as the worst-case scenario.

2) We are using the Processor: AM6442BSDGHAALV whose Minimum Input Voltage of VDD_CORE (0.75V Typical) is 0.715V. whose minimum ripple is calculated to be -4.66667%.

3) Now ripple margin is calculated to be (-4.66667) - (-1.5) = -3.16667%

4) Furthermore -3.16667 is divided by 2 to have a stringent Ztarget for VDD_CORE i,e.: (-3.16667 / 2) = 1.58333% rounding off as 1.6%.

Now while substituting the above values to the Ztarget formula, we get:

                 Ztarget = (0.75V x 1.6%) / (0.5 x 2A) = 12mΩ.

But when we refer the TI document "SPRAC76G – NOVEMBER 2022 – REVISED FEBRUARY 2024" (Sitara Processor Power Distribution Networks: Implementation and Analysis) in Table 7-7 we see the different Ztarget values, below is the snapshot of the same for your reference.

Can you please explain us how did TI arrive to the different Ztarget values as given below?

                       10mΩ for ≤1MHz

                       34mΩ for 1-20 MHz 

                       35mΩ for 20-50MHz

For arriving to the above values, was the input voltage to VDD_CORE considered as an Ideal Voltage as 0.75V?

For AM64x we did not use the load transient approach for calculating target -Z. We extracted the impedance plot for our EVM (which was found to pass characterization) and provided the AC impedance as targets for the different frequency bands.

 Also note that a target of 1.6% will be excessively stringent for all frequency bands. Typically we use:

 3% for < 1MHZ

5% for 1 – 20 MHz

10% for 20-50 MHz

That is because the effectiveness of board decap will be much diminished for higher frequency transients due to the additional pkg/brd inductance seen by the decaps. The higher freq transients will depend on effectiveness of on-die decap to be adequately suppressed.

Inputs on PDN 

(+) [FAQ] AM62A3-Q1: AM62A3-Q1 PDN Power SI SIMULATION Questions - Processors forum - Processors - TI E2E support forums

Please refer below inputs i received:

Please note these are only recommendations and they need to contact their EDA vendor on what works best for their specific simulation environment.
1、Do I need to separate VDD_CORE-1 to 17 for simulation, or use VDD_CORE as a Port?
TI>> You can lump all VDD_CORE BGAs together as a single terminal for the port
2、Do I need to include the PMIC FB loop in the simulation?
TI>> If you are simulating only for AC impedance (target impedance checks) this is not required. The board layout from the inductor onwards (inductor not included) can be modeled and PMIC FB loop can be studied separately.
3、 Is the simulation starting frequency from 1Hz or from a minimum of 100kHz for the capacitor S2P?
TI>> There should be some DC frequency points added. Please check with your EDA vendor on the exact setup and simulation points needed to generate causal models.

I added additional inputs related to PDN and decoupling capacitors for reference.

The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth

PCB design & Dcap scheme combine to form your board's Power Distribution Network (PDN) that should meet recommended SoC PI performance targets for robust processor operations. Each PCB design has a "unique finger-print" based upon component placements, power & Gnd routing, layer assignments, via qtys & locations, Dcap mounting & loop inductance, Dcap parameters, etc. As a result, an optimized Dcap scheme will vary from one PCB design to another but should provide a system PDN that meets PI performance targets when combined together. Similarly, the PI simulation tools can impact the estimated ZvsF response values, especially above 3.0MHz where non-3D extraction tools can return better Z values (10-15% less than more accurate 3D tools). This ican be due to a non-3D tool is only extracting a PCB's X & Y design elements & assuming a power & Gnd via inductances.  Due to the 3D nature of current flow across & through a PCB from power & Gnd planes on different PCB layers, a 3D extraction gives a more accurate series inductance estimate needed to more accurately model power & Gnd vias which leads to a more accurate power rail impedance (ZvsF) response

it would be difficult to comment on reducing the amount of decoupling caps without going through the exercise ourselves.  That said, you can likely prioritize the high-current and sensitive analog rails, then look to share bypass caps when you hit space constraints.  Having decap as close to the BGA as possible will reduce inductance and improve their efficacy (two supply vias with a shared decap would be better than a decap located far away in most circumstances). 

Please be aware that each PCB design is unique and may need different Dcap scheme to meet recommended PI parameter targets

Regarding decoupling capacitors, the recommendation is to start with the EVMs decoupling and then optimize (if needed) based on your power simulation results.

For the placement of the Caps and values, we would still recommend using the EVM as a reference along with the PDN document.

SK uses an EMI Filter at 1uF, can I replace it with a general ceramic capacitor?

The SK performance has been tested with 3-T terminal caps.

You may have to add multiple 2-T caps for each cap and perform simulations to finalize the values.

(50) [DRA829] SOM Schematic has "NFM15HC105D0G" and "NFM18HC106D0G" - Processors forum - Processors - TI E2E support forums

(49) TDA4VH-Q1: TDA4VH Power 3T filter capacitor questions - Processors forum - Processors - TI E2E support forums

PDN application note

https://www.ti.com/lit/an/sprac76g/sprac76g.pdf

Regards,

Sreenivasa

Hello Board designers 

Queries regarding reducing decaps for the VDD_CORE and other supplies:

Customer is looking to reduce the decaps on the VDD_CORE. I am suggesting them to follow the PDN.

In case customer performs the required simulation and depending on the layout, I guess it should be possible to reduce the caps.

Yes that is correct. They can reduce the number of decaps but they need to ensure they follow the PDN app note guidelines and meet the target impedance requirements for VDD_CORE.

 Regards,

Sreenivasa

Hi Board designers,

Refer below inputs for PMIC power sequencing.

AM6421: Sudden Loss of Power Impact on Power Down Sequence

(+) AM6421: Sudden Loss of Power Impact on Power Down Sequence - Processors forum - Processors - TI E2E support forums

 As stated in the AM64x datasheet, "The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at 0.75V". AM64 was characterized under operating conditions so we cannot guarantee the expected operation beyond the conditions specified in the datasheet. PCB designers are responsible for validating and characterizing the SoC under specific use case conditions to confirm it meets the application system level requirements. 

Handling uncontrolled power-down requires additional considerations in the design like adding additional input capacitance or a discrete supervisor to monitor voltage at the power source and trigger an OFF request before PMIC loses power. Here is an example FAQ for reference: https://e2e.ti.com/blogs_/b/powerhouse/posts/how-to-meet-power-sequencing-requirements-with-a-pmic.

Another option to consider to mitigate the sequencing concerns during uncontrolled power-down is running the main CORE at 0.85V which allows to combine VDD_CORE and VDDR_CORE together. In this scenario both rails are supplied by the same PMIC DCDC regulator.

Regards,

Sreenivasa

Hi Board designers, 

PMIC capacitor and feedback recommendations

PMIC - feed back and jumper or 0R provisioning 

Regards,

Sreenivasa