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TDA4VM-Q1: SR 2.0 Booting Fail Issue Occurred at High Temp Situation

Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VM,

Tool/software:

Dear Expert,

We are experiencing a critical boot failure with TDA4VM SR2.0 in high-temperature conditions. Here are the specific details

  • Device: TDA4VM-Q1
  • Versions tested: SR1.1 and SR2.0
  • Test environment: ON/OFF Test in Chamber at 85°C ( 1min ON / 1min OFF )

Observed Behavior

  • SR1.1 board: Normal operation (Current draw ~2.0A)
  • SR2.0 board: Boot failure (Current draw ~1.4A)

Test Results

  1. Room Temperature:
    • Both SR1.1 and SR2.0 operate normally
  2. High Temperature (85°C):
    • SR2.0 fails after 1-2 operations
    • AP stops functioning
    • OSPI read failure occurs
    • Verified on two different SR2.0 boards with identical results

Possibility Technical Analysis

  • The issue appears to be related to OSPI block impedance changes at high temperatures
  • The automatic tuning range seems to be exceeded, causing read failures
  • Possible internal impedance variations between SR1.1 and SR2.0

Questions

  1. Is this a known issue with SR2.0 in high-temperature conditions?
  2. Are there any recommended modifications for the OSPI interface resistance values?
  3. What are the specific differences between SR1.1 and SR2.0 regarding the OSPI block characteristics?
  4. Are there any firmware updates or workarounds available for this issue?

We would greatly appreciate your guidance on resolving this critical issue affecting our production environment.

 

  • In additionally, we will share the log that we acquired.

    We check AP-MCU uart, it was confirmed that NOR flash read is failed. (AP-VPU uart does not show anything)

    Log:

    [2024-12-11 13:25:51.879] SBL Revision: 01.00.10.00 (Dec 2 2024 - 19:15:31)
    [2024-12-11 13:25:51.925]
    [2024-12-11 13:25:51.925] [BOOT_PART] first space booting start
    [2024-12-11 13:25:51.974]
    [2024-12-11 13:25:52.037] TIFS ver: 20.8.7-v2020.08d_plus_inf_tmout
    [2024-12-11 13:25:52.088]
    [2024-12-11 13:25:52.088]
    [2024-12-11 13:25:52.088]
    [2024-12-11 13:25:52.102] ## Clock monitoring disable ..
    [2024-12-11 13:25:52.134]
    [2024-12-11 13:25:52.166] Board_flashRead failed!

  • Hi,

    Could you please let us know which SDK release you are using? 

    Regards,

    Brijesh

  • Hi,

    We use SDK 7.1 (pdk jacinto 07.01)

  • Hi,

    Also can you please enable profile code in the PHY tune algorithm and share the output from this algorithm? We want to see if tuning was successful and if it is not, where does it fail? 

    Regards,

    Brijesh

  • Hi Sungjun

    You can get the log regarding the OSPI tuning by enabling below macro in nor_spi_phy_tune.c

    //#undef NOR_SPI_TUNE_DEBUG

    #define NOR_SPI_TUNE_DEBUG

    Could you please try and share the log?

    Thank you.

    Regards,

    Johnny

  • Hi,

    This is the log after #define NOR_SPI_TUNE_DEBUG

    SBL Revision: 01.00.10.00 (Dec 24 2024 - 12:03:38)
    [BOOT_PART] first space booting start
    TIFS ver: 20.8.7-v2020.08d_plus_inf_tmout

    ## Clock monitoring disble ...


    Fast Tuning at temperature 41C
    Bottom left found at txDLL,rxDLL of 3,0 to 17,10, and a rdDelay of 1
    Top Right found at txDLL,rxDLL of 18,11 to 52,39, and a rdDelay of 2
    Tuning was complete in 109 steps
    Tuning PHY to txDLL,rxDLL of 36,26 and rdDelay of 2


    Fast Tuning at temperature 42C


    Fast Tuning at temperature 43C
    Bottom left found at txDLL,rxDLL of 3,0 to 17,10, and a rdDelay of 1
    Top Right found at txDLL,rxDLL of 18,11 to 52,39, and a rdDelay of 2
    Tuning was complete in 109 steps
    Tuning PHY to txDLL,rxDLL of 36,26 and rdDelay of 2


    Fast Tuning at temperature 43C


    Fast Tuning at temperature 43C


    Fast Tuning at temperature 43C


    Fast Tuning at temperature 43C


    Fast Tuning at temperature 43C


    Fast Tuning at temperature 44C


    Fast Tuning at temperature 44C
    [FW_PART] part_A space booted, 41cace50
    Boot App: Started at 60 usec
    Boot App: Total Num booted cores = 8
    Boot App: Booted Core ID #6 at 552781 usecs
    Boot App: Booted Core ID #7 at 552988 usecs
    Boot App: Booted Core ID #8 at 754151 usecs
    Boot App: Booted Core ID #9 at 754359 usecs
    Boot App: Booted Core ID #10 at 754543 usecs
    Boot App: Booted Core ID #11 at 754721 usecs
    Boot App: Booted Core ID #12 at 755383 usecs
    Boot App: Booted Core ID #0 at 1492308 usecs

    MCU Boot Task started at 59 usecs and finished at 82109457 usecs

    Thanks.

  • Hi,

    But this log seems from successful run. I see that all cores are booting fine and boot finishes with "MCU Boot Task started at 59 usecs and finished at 82109457 usecs" message. 

    Do you have similar log when booting fails?

    Regards,

    Brijesh

  • Hi,

    Sorry, the log above was checked at room temperature.

    At high temperatures, the following logs occur.

    SBL Revision: 01.00.10.00 (Dec 24 2024 - 12:03:38)
    [BOOT_PART] first space booting start
    TIFS ver: 20.8.7-v2020.08d_plus_inf_tmout

    ## Clock monitoring disble ...


    Fast Tuning at temperature 54C
    rxLow and rxHigh are on the same rdDelay
    Unable to find TX Max
    Board_flashRead failed!

    We test by raising the temperature to 85 degrees, but the board fails to boot from 54 degrees.
    The failure log at maximum temperature is as follows.

    SBL Revision: 01.00.10.00 (Dec 24 2024 - 12:03:38)
    [BOOT_PART] first space booting start
    TIFS ver: 20.8.7-v2020.08d_plus_inf_tmout

    ## Clock monitoring disble ...


    Fast Tuning at temperature 99C
    rxLow and rxHigh are on the same rdDelay
    Unable to find TX Max
    Board_flashRead failed!

    Thanks.

  • Hi Sungjun Lim,

    In the file packages\ti\board\src\flash\nor\ospi\nor_spi_phy_tune.h, can you please try increasing the window range, as shown below and see if it helps in finding TX Max?

    #define NOR_SPI_PHY_TXDLL_LOW_WINDOW_START (0U)
    #define NOR_SPI_PHY_TXDLL_LOW_WINDOW_END (127U)

    #define NOR_SPI_PHY_TXDLL_HIGH_WINDOW_START (0U)
    #define NOR_SPI_PHY_TXDLL_HIGH_WINDOW_END (127U)

    Regards,

    Brijesh

  • Hello Brijesh

    I'm currently working now to re-test using new sample which has been made from mass production set-up.

    That's why the test result is being postponed now.

    When i get the new test result, i will update this query with the result.

    As you know well, Korean New Years holiday will start this weekend to nextweek.

    So I share the result in the 1st week of February.

    Thanks.

  • Thanks Jisung, i will wait for your update. 

  • Jisung, please provide an update, we close threads with no update after 30 days, thank you, Dave C

  • Hello Dave,

    Thanks for your concern to this issue.

    Current situation is the below.

    All samples were applied SR2.0 TDA4VM.

    • Total Sample Quantity: 8ea
    • Test Set-Up
      • Temp : +85
      • ON / OFF : 2min (each)
    • Test Result
      • PASS : 6ea
      • Fail : 2ea

    So, we applied the TX MAX Value that Brijesh provided to the failed sample and conducted the test.

    The result was PASS (under the same test environment).

    However, we observed that the booting time increased by about 20ms.

    What else can we try?

  • Hi Jisung,

    We need to now understand for which window it is passing and then have window range around this passing point. This should help in reducing the boot time. 

    So can we please first enable debug profile in the OSPI to figure out passing point?

    Regards,

    Brijesh

  • Hello Sungjun,

    Could you please help me to Brijesh's request?

    Hello Brijesh,

    Can you explain to us what exactly needs to be done?

    Thx.

  • Please enable the logging in the SPI tuning algorithm. 

    Regards,

    Brijesh

  • Hi Brijesh,

    You means

        | Enabling below macro in nor_spi_phy_tune.c

        | //#undef NOR_SPI_TUNE_DEBUG

        | #define NOR_SPI_TUNE_DEBUG

    that Johnny said before?

    Thanks.

  • Hi Sungjun Lim,

    Yes, can you please enable this flag and run the test case in working case? Lets get the window position where it is passing. 

    Regards,

    Brijesh

  • Hello 

    The flag which you requested in this query was enable already.

    You need Full log when the TDA4VM is waking-Up?

    If yes, 

    Jeayoung, please provide the log which the flag enabled.

    thx

  • Yes, i require full log to figure out at which window location it is passing. 

    Regards,

    Brijesh

  • Hello

    Here is Full log that the test case in working case

    [2025-02-13 18:42:48.005] ��SBL Revision: 01.00.10.00 (Jan 15 2025 - 16:20:47)
    [2025-02-13 18:42:48.305] [BOOT_PART] first space booting start
    [2025-02-13 18:42:48.423] TIFS ver: 20.8.7-v2020.08d_plus_inf_tmout
    [2025-02-13 18:42:48.460]
    [2025-02-13 18:42:48.460] ## Clock monitoring disble ...
    [2025-02-13 18:42:48.549]
    [2025-02-13 18:42:48.549]
    [2025-02-13 18:42:48.549] Fast Tuning at temperature 83C
    [2025-02-13 18:42:48.579] Bottom left found at txDLL,rxDLL of 3,0 to 10,5, and a rdDelay of 1
    [2025-02-13 18:42:48.664] Top Right found at txDLL,rxDLL of 11,6 to 48,35, and a rdDelay of 2
    [2025-02-13 18:42:48.727] Tuning was complete in 249 steps
    [2025-02-13 18:42:48.755] Tuning PHY to txDLL,rxDLL of 32,22 and rdDelay of 2
    [2025-02-13 18:42:48.823]
    [2025-02-13 18:42:48.823]
    [2025-02-13 18:42:48.823] Fast Tuning at temperature 84C
    [2025-02-13 18:42:49.008]
    [2025-02-13 18:42:49.026]
    [2025-02-13 18:42:49.026] Fast Tuning at temperature 84C
    [2025-02-13 18:42:49.054] Bottom left found at txDLL,rxDLL of 3,0 to 10,5, and a rdDelay of 1
    [2025-02-13 18:42:49.121] Top Right found at txDLL,rxDLL of 11,6 to 48,35, and a rdDelay of 2
    [2025-02-13 18:42:49.206] Tuning was complete in 249 steps
    [2025-02-13 18:42:49.238] Tuning PHY to txDLL,rxDLL of 32,22 and rdDelay of 2
    [2025-02-13 18:42:49.274]
    [2025-02-13 18:42:49.288]
    [2025-02-13 18:42:49.288] Fast Tuning at temperature 84C
    [2025-02-13 18:42:49.427]
    [2025-02-13 18:42:49.427]
    [2025-02-13 18:42:49.427] Fast Tuning at temperature 85C
    [2025-02-13 18:42:49.456]
    [2025-02-13 18:42:49.479]
    [2025-02-13 18:42:49.479] Fast Tuning at temperature 85C
    [2025-02-13 18:42:49.625]
    [2025-02-13 18:42:49.625]
    [2025-02-13 18:42:49.625] Fast Tuning at temperature 85C
    [2025-02-13 18:42:49.667]
    [2025-02-13 18:42:49.667]
    [2025-02-13 18:42:49.667] Fast Tuning at temperature 86C
    [2025-02-13 18:42:49.718]
    [2025-02-13 18:42:49.718]
    [2025-02-13 18:42:49.718] Fast Tuning at temperature 85C
    [2025-02-13 18:42:49.743]
    [2025-02-13 18:42:49.765]
    [2025-02-13 18:42:49.765] Fast Tuning at temperature 86C
    [2025-02-13 18:42:50.312] [FW_PART] part_A space booted, a
    [2025-02-13 18:42:58.364] �: Started at 61 usec
    [2025-02-13 18:42:58.393] Boot App: Total Num booted cores = 8
    [2025-02-13 18:42:58.425] Boot App: Booted Core ID #6 at 553559 usecs
    [2025-02-13 18:42:58.475] Boot App: Booted Core ID #7 at 553765 usecs
    [2025-02-13 18:42:58.509] Boot App: Booted Core ID #8 at 754528 usecs
    [2025-02-13 18:42:58.561] Boot App: Booted Core ID #9 at 754734 usecs
    [2025-02-13 18:42:58.609] Boot App: Booted Core ID #10 at 754919 usecs
    [2025-02-13 18:42:58.667] Boot App: Booted Core ID #11 at 755102 usecs
    [2025-02-13 18:42:58.715] Boot App: Booted Core ID #12 at 755753 usecs
    [2025-02-13 18:42:58.746] Boot App: Booted Core ID #0 at 1485309 usecs
    [2025-02-13 18:42:58.803]
    [2025-02-13 18:42:58.814] MCU Boot Task started at 59 usecs and finished at 82057259 usecs

  • Hello Jisung Hyun,

    Could you try to experiment with modifying #define *_END values as below to reduce boot time?

            #define NOR_SPI_PHY_TXDLL_LOW_WINDOW_START (0U)
            #define NOR_SPI_PHY_TXDLL_LOW_WINDOW_END (63U)      

            #define NOR_SPI_PHY_TXDLL_HIGH_WINDOW_START (63U)
            #define NOR_SPI_PHY_TXDLL_HIGH_WINDOW_END (0U)

    regards, Lloyd

  • Hello Jisung Hyun, 

    Do you have any update on the experiment with modifying tuning range? 

    Just for the double check, may I ask you if the below patch is used on your SDK?  

     https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_PDK_2D00_9328_2D00_OSPI_2D00_Binary_2D00_search_2D00_instead_2D00_of_2D00_linear_2D00_search.patch

    regards,

    Lloyd

  • Dear Lloyd,

    Please find the test results below, following T.I's recommendations.

    • Device: TDA4VM-Q1
    • Versions tested:  SR2.0
    • Test environment: ON/OFF cycling in Chamber at 85°C ( 1min ON / 1min OFF )
    • Quantity : 2ea ( Failure Sample in intial setting)
    • Test Duration : 144h ( 1week )
    • Test Result
      • Operating : Yes
      • Boot Time
        • Initial : 1.23s ( Boot failed )
        • 1st modification: 1.248s ( No Issue )
        • 2nd modification: 1.247s ( No Issue )

    Hello Sungjun,

    Could you please check Lloyd's question regarding whether the SDK patch has been applied?

    Thanks.

  • Hello

    Thanks for sharing the result. 

    May I ask you to share the log by enabling the macro in nor_spi_phy_tune.c for the 2nd modification ? 

    regards,

    Lloyd

  • Hello Jaeyoung,

    If you have any logs obtained from this test, please share them in this thread.

    Thanks,

  • Hello, Lloyd Hwang

    Here is the Log that use 2nd modification.

    Thanks.

    [2025-04-16 16:56:12.334] �SBL Revision: 01.00.10.00 (Apr 9 2025 - 11:14:41)
    [2025-04-16 16:56:12.646]
    [2025-04-16 16:56:12.646] [BOOT_PART] first space booting start
    [2025-04-16 16:56:12.680]
    [2025-04-16 16:56:12.747] TIFS ver: 20.8.7-v2020.08e_j7es_pg2.0_nto
    [2025-04-16 16:56:12.796]
    [2025-04-16 16:56:12.812]
    [2025-04-16 16:56:12.812]
    [2025-04-16 16:56:12.812] ## Clock monitoring disble ...
    [2025-04-16 16:56:12.845]
    [2025-04-16 16:56:13.835] [FW_PART] part_A space booted, a
    [2025-04-16 16:56:13.860]
    [2025-04-16 16:56:21.862] Boot App: Started at 60 usec
    [2025-04-16 16:56:21.901]
    [2025-04-16 16:56:21.901] Boot App: Total Num booted cores = 8
    [2025-04-16 16:56:21.933]
    [2025-04-16 16:56:21.933] Boot App: Booted Core ID #6 at 248613 usecs
    [2025-04-16 16:56:21.985]
    [2025-04-16 16:56:21.985] Boot App: Booted Core ID #7 at 248819 usecs
    [2025-04-16 16:56:22.034]
    [2025-04-16 16:56:22.034] Boot App: Booted Core ID #8 at 369795 usecs
    [2025-04-16 16:56:22.083]
    [2025-04-16 16:56:22.083] Boot App: Booted Core ID #9 at 370001 usecs
    [2025-04-16 16:56:22.118]
    [2025-04-16 16:56:22.118] Boot App: Booted Core ID #10 at 370194 usecs
    [2025-04-16 16:56:22.170]
    [2025-04-16 16:56:22.170] Boot App: Booted Core ID #11 at 370374 usecs
    [2025-04-16 16:56:22.217]
    [2025-04-16 16:56:22.217] Boot App: Booted Core ID #12 at 371024 usecs
    [2025-04-16 16:56:22.270]
    [2025-04-16 16:56:22.270] Boot App: Booted Core ID #0 at 973309 usecs
    [2025-04-16 16:56:22.300]
    [2025-04-16 16:56:22.310]
    [2025-04-16 16:56:22.310]
    [2025-04-16 16:56:22.310] MCU Boot Task started at 59 usecs and finished at 75501334 usecs
    [2025-04-16 16:56:22.383]
    [2025-04-16 16:56:22.383]
    [2025-04-16 17:00:12.575] SBL Revision: 01.00.10.00 (Apr 9 2025 - 11:14:41)
    [2025-04-16 17:00:12.633]
    [2025-04-16 17:00:12.633] [BOOT_PART] first space booting start
    [2025-04-16 17:00:12.671]
    [2025-04-16 17:00:12.739] TIFS ver: 20.8.7-v2020.08e_j7es_pg2.0_nto
    [2025-04-16 17:00:12.787]
    [2025-04-16 17:00:12.804]
    [2025-04-16 17:00:12.804]
    [2025-04-16 17:00:12.804] ## Clock monitoring disble ...
    [2025-04-16 17:00:12.834]
    [2025-04-16 17:00:13.814] [FW_PART] part_A space booted, a
    [2025-04-16 17:00:13.852]
    [2025-04-16 17:00:21.863] Boot App: Started at 61 usec
    [2025-04-16 17:00:21.892]
    [2025-04-16 17:00:21.892] Boot App: Total Num booted cores = 8
    [2025-04-16 17:00:21.925]
    [2025-04-16 17:00:21.925] Boot App: Booted Core ID #6 at 248813 usecs
    [2025-04-16 17:00:21.976]
    [2025-04-16 17:00:21.976] Boot App: Booted Core ID #7 at 249019 usecs
    [2025-04-16 17:00:22.026]
    [2025-04-16 17:00:22.026] Boot App: Booted Core ID #8 at 371927 usecs
    [2025-04-16 17:00:22.075]
    [2025-04-16 17:00:22.075] Boot App: Booted Core ID #9 at 372137 usecs
    [2025-04-16 17:00:22.109]
    [2025-04-16 17:00:22.109] Boot App: Booted Core ID #10 at 372324 usecs
    [2025-04-16 17:00:22.158]
    [2025-04-16 17:00:22.158] Boot App: Booted Core ID #11 at 372503 usecs
    [2025-04-16 17:00:22.208]
    [2025-04-16 17:00:22.208] Boot App: Booted Core ID #12 at 373162 usecs
    [2025-04-16 17:00:22.259]
    [2025-04-16 17:00:22.259] Boot App: Booted Core ID #0 at 973310 usecs
    [2025-04-16 17:00:22.292]
    [2025-04-16 17:00:22.316]
    [2025-04-16 17:00:22.316]
    [2025-04-16 17:00:22.316] MCU Boot Task started at 60 usecs and finished at 75500317 usecs

  • Hello 

    Thanks a lot. Can I ask you the log by enabling the macro in nor_spi_phy_tune.c for the 2nd modification as below? 

           //#undef NOR_SPI_TUNE_DEBUG

           #define NOR_SPI_TUNE_DEBUG

    Regards,

    Lloyd

  • Hello, Lioyd Hwang.

    Here is the log that you request the macro.

    Pleas Check this log.

    [2025-04-24 12:56:07.893] [BOOT_PART] first space booting start
    [2025-04-24 12:56:08.009] TIFS ver: 20.8.7-v2020.08e_j7es_pg2.0_nto
    [2025-04-24 12:56:08.049]
    [2025-04-24 12:56:08.049] ## Clock monitoring disble ...
    [2025-04-24 12:56:08.137]
    [2025-04-24 12:56:08.137]
    [2025-04-24 12:56:08.137] Fast Tuning at temperature 91C
    [2025-04-24 12:56:08.156] Bottom left found at txDLL,rxDLL of 3,0 to 10,5, and a rdDelay of 1
    [2025-04-24 12:56:08.263] Top Right found at txDLL,rxDLL of 11,6 to 49,36, and a rdDelay of 2
    [2025-04-24 12:56:08.311] Tuning was complete in 247 steps
    [2025-04-24 12:56:08.344] Tuning PHY to txDLL,rxDLL of 33,23 and rdDelay of 2
    [2025-04-24 12:56:08.412]
    [2025-04-24 12:56:08.412]
    [2025-04-24 12:56:08.412] Fast Tuning at temperature 92C
    [2025-04-24 12:56:08.600]
    [2025-04-24 12:56:08.600]
    [2025-04-24 12:56:08.600] Fast Tuning at temperature 93C
    [2025-04-24 12:56:08.648] Bottom left found at txDLL,rxDLL of 3,0 to 10,5, and a rdDelay of 1
    [2025-04-24 12:56:08.709] Top Right found at txDLL,rxDLL of 11,6 to 49,36, and a rdDelay of 2
    [2025-04-24 12:56:08.776] Tuning was complete in 247 steps
    [2025-04-24 12:56:08.811] Tuning PHY to txDLL,rxDLL of 33,23 and rdDelay of 2
    [2025-04-24 12:56:08.859]
    [2025-04-24 12:56:08.859]
    [2025-04-24 12:56:08.859] Fast Tuning at temperature 93C
    [2025-04-24 12:56:09.004]
    [2025-04-24 12:56:09.004]
    [2025-04-24 12:56:09.004] Fast Tuning at temperature 94C
    [2025-04-24 12:56:09.060]
    [2025-04-24 12:56:09.060]
    [2025-04-24 12:56:09.060] Fast Tuning at temperature 93C
    [2025-04-24 12:56:09.209]
    [2025-04-24 12:56:09.209]
    [2025-04-24 12:56:09.209] Fast Tuning at temperature 94C
    [2025-04-24 12:56:09.258]
    [2025-04-24 12:56:09.258]
    [2025-04-24 12:56:09.258] Fast Tuning at temperature 94C
    [2025-04-24 12:56:09.292]
    [2025-04-24 12:56:09.292]
    [2025-04-24 12:56:09.292] Fast Tuning at temperature 94C
    [2025-04-24 12:56:09.337]
    [2025-04-24 12:56:09.337]
    [2025-04-24 12:56:09.337] Fast Tuning at temperature 94C
    [2025-04-24 12:56:09.913] [FW_PART] part_B space booted, b
    [2025-04-24 12:56:17.950] Boot App: Started at 61 usec
    [2025-04-24 12:56:17.977] Boot App: Total Num booted cores = 8
    [2025-04-24 12:56:18.013] Boot App: Booted Core ID #6 at 553729 usecs
    [2025-04-24 12:56:18.060] Boot App: Booted Core ID #7 at 553936 usecs
    [2025-04-24 12:56:18.108] Boot App: Booted Core ID #8 at 755672 usecs
    [2025-04-24 12:56:18.144] Boot App: Booted Core ID #9 at 755878 usecs
    [2025-04-24 12:56:18.198] Boot App: Booted Core ID #10 at 756069 usecs
    [2025-04-24 12:56:18.239] Boot App: Booted Core ID #11 at 756252 usecs
    [2025-04-24 12:56:18.273] Boot App: Booted Core ID #12 at 756899 usecs
    [2025-04-24 12:56:18.327] Boot App: Booted Core ID #0 at 1488309 usecs
    [2025-04-24 12:56:18.374]
    [2025-04-24 12:56:18.410] MCU Boot Task started at 59 usecs and finished at 82076004 usecs

    Thank you.

  • Hi Lloyd, Mr Jaeyong Yoo,

    I am bit confused with the above logs. 

    There are three complete logs shared in this forum. 

    - In the first log, shared around 2months back at below link, i see boot time is completed by around 82057259 usecs. But tifs version mentioned here is 20.8.7-v2020.08d_plus_inf_tmout. We dont use this TIFS on ES2.0. So is this incorrect log? or is it from ES1.1? 

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1452322/tda4vm-q1-sr-2-0-booting-fail-issue-occurred-at-high-temp-situation/5682153#5682153

    - The second logs, shared at around 13days at below link, has correct TIFS version ie 20.8.7-v2020.08e_j7es_pg2.0_nto, but here boot finishes in 75501334 usecs. I guess we change the window to half, isn't it?

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1452322/tda4vm-q1-sr-2-0-booting-fail-issue-occurred-at-high-temp-situation/5781088#5781088

    - The third log, shared around 6 days back at below link, has correct TIFS version, ie 20.8.7-v2020.08e_j7es_pg2.0_nto, but here the boot finishes in 82076004 usecs.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1452322/tda4vm-q1-sr-2-0-booting-fail-issue-occurred-at-high-temp-situation/5794064#5794064

    So what's changed between second and third log? Can you please confirm that you have reduced the window size in the third log? Because we can clearly see boot time reduction in the second log. 

    Regards,

    Brijesh

  • Hi, Brijesh Jadav.

    Here are my answers below

    1. All Logs are ES2.0 Log.

    2. Second and Third log is same borad, except enabling SW macros below for TI request.

    -> enabling the macro in nor_spi_phy_tune.c for the 2nd modification as below

           //#undef NOR_SPI_TUNE_DEBUG

           #define NOR_SPI_TUNE_DEBUG

    3. I'm not sure but, TI has supplied us with a software update optimized for faster boot time.
    So, TI will know better that the window has been reduced to half

  • hi Yoo,

    But does it mean the increase in boot time is because of the increased log? If the boot finishes in 75501334 usec, is it correct and matching with ES1.1? 

    Regards,

    Brijesh

  • Hi Yoo, please respond to Brijesh, we will close the thread if there is no further update, Dave C

  • Closing due to no further update, simply reply to re-open if further support is needed, Dave C