Hi I'm trying to implement the chip level interrupts for using the SPI/I2C for send/receive events, the problem I seem to be having is that the interrupts don't fire more than once.
/* Interrupt CorePac IDs */
//#define I2C_CORE_INTC CSL_GEM_INTC0_OUT_64_PLUS_10_MUL_N // CorePac Interrupt to route Chip Level Interrupt to (OUT2 0x3c = 60)
//#define I2C_CORE_INTC_CHANNEL (64 + 10 * DNUM)
#define I2C_CORE_INTC CSL_GEM_INTC0_OUT4 // CorePac Interrupt to route Chip Level Interrupt to (OUT2 0x3c = 60)
#define I2C_CORE_INTC_CHANNEL 4
/* Interrupt Chip Level IDs */
#define I2C_CHIP_INTC CSL_INTC0_I2CINT
#define I2C_CHIP_INTC_RX CSL_INTC0_I2CREVT
#define I2C_CHIP_INTC_TX CSL_INTC0_I2CXEVT
bool ti_interrupt_init() {
uint i;
long long start = ti_clock_count();
CSL_Status intStat;
Context.numEvtEntries = INTERRUPT_EVENTS;
Context.eventhandlerRecord = (CSL_IntcEventHandlerRecord*) &(Record);
for(i = 0; i < 7; i++) {
switch(i) {
case 0:
intStat = CSL_intcInit(&(gIntc.Context));
break;
case 1:
intStat = CSL_intcExcepAllClear(CSL_INTC_EXCEP_0TO31,0xFFFF); // clear all exceptions
break;
case 2:
intStat = CSL_intcExcepAllClear(CSL_INTC_EXCEP_32TO63,0xFFFF);
break;
case 3:
intStat = CSL_intcExcepAllClear(CSL_INTC_EXCEP_64TO95,0xFFFF);
break;
case 4:
intStat = CSL_intcExcepAllClear(CSL_INTC_EXCEP_96TO127,0xFFFF);
break;
case 5:
intStat = CSL_intcGlobalNmiEnable(); // global NMI enable
break;
case 6:
intStat = CSL_intcGlobalEnable(NULL); // global intC enable
break;
default:
break;
}
if(intStat != CSL_SOK) {
/* Failed CSL Call */
printf("Interrupt Initialization Failed - %d \n", i);
return false;
}
}
/* Initialize the chip level INTC CSL handle. */
cphnd = CSL_CPINTC_open(0);
if (cphnd == 0) {
printf("Cannot initialize CPINTC\n");
return false;
}
return true;
}
bool twi_interrupt_setup(void) {
CSL_IntcParam vectId;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcObj intcObj0;
/* Disable all host interrupts. */
CSL_CPINTC_disableAllHostInterrupt(cphnd);
/* Configure no nesting support in the CPINTC Module. */
CSL_CPINTC_setNestingMode(cphnd, CPINTC_NO_NESTING);
/* Clear CSL_INTC0_VUSR_INT_O */
CSL_CPINTC_clearSysInterrupt(cphnd, I2C_CHIP_INTC);
/* Enable it */
CSL_CPINTC_enableSysInterrupt(cphnd, I2C_CHIP_INTC);
CSL_CPINTC_mapSystemIntrToChannel(cphnd, I2C_CHIP_INTC, I2C_CORE_INTC_CHANNEL);
/* Do not need to use CSL_CPINTC_mapChannelToHostInterrupt because the mapping is static
* such that channel and host interrupt are the same
*/
/* Enable it */
CSL_CPINTC_enableHostInterrupt(cphnd, I2C_CORE_INTC_CHANNEL);
CSL_CPINTC_enableAllHostInterrupt(cphnd);
/* Opening a handle for CIC out 0 onto CPU vector 9 */
vectId = I2C_INTC_VECTID;
intcI2cHnd = CSL_intcOpen (&intcObj0, I2C_CORE_INTC, &vectId, NULL);
EventRecord.handler = ti_i2c_isr;
EventRecord.arg = (void *)I2C_CORE_INTC;
CSL_intcPlugEventHandler(intcI2cHnd, &EventRecord);
CSL_intcHwControl(intcI2cHnd, CSL_INTC_CMD_EVTCLEAR, NULL);
CSL_intcHwControl(intcI2cHnd, CSL_INTC_CMD_EVTENABLE, NULL);
return true;
}
