Tool/software:
Hello Support-Team,
we have developed a porting layer for TIOVX on our own OS and have mapped until recently the TIOVX Obj Descriptor, Log RT, and App Log segments uncached.
Due to some restrictions we would like to map these segments as cache coherent memory.
If I understood the answer to the linked question correctly the only thing to be done on the A72 CPU is to map those segments as shareable.
We tried both the inner shareable attribute as well as the outer shareable attribute, but ran into effects that look like cache coherency is not given.
For example, when running the TIOVX conformance test suite some runs lead to the following output:
[ -------- ] tests from tivxTestKernelsNotNot
[ RUN 0001 ] tivxTestKernelsNotNot.Sizes/0/640x480 ...
[C7x_2 ] 15.527368 s: VX_ZONE_ERROR:[ownTargetCmdDescHandler:1115] object descriptor type is invalid
This leads to our assumption that the initialization of the object descriptor array does not reach the C7X, when mapping the array cached.
Is there any other configuration at the MSMC or the MMU to be done to ensure the coherency between all processors and is there a way to confirm that?
We are booting from u-boot and do not touch the MSMC in any way in our OS.
Thank you and kind regards,
Marco