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AM6548: PRU clock setting

Part Number: AM6548


Tool/software:

Hi Ti,

We are using AM6548 with Linux RT SDK now and we have our program running inside PRU.

Below is our IEP setting and we use CT_IEP0 for PRU0_0 and PRU2_1.

void IEPTimer_init(void)
{

/* Set PRU Sync-to-VCLK Mode, Clock speed 250MHz*/
CT_CFG.core_sync_reg_bit.core_vbusp_sync_en = 1;

/* Set IEP as sync mode, the clock is 250MHz*/
CT_CFG.iepclk_reg_bit.iep_ocp_clk_en = 1;

/* Enable shadow mode*/
IEPCounter.cmp_cfg_reg_bit.shadow_en = 1;

/* Disable counter */
IEPCounter.global_cfg_reg_bit.cnt_enable = 0;

/* Reset Count register */
IEPCounter.count_reg0 = 0xFFFFFFFF;
IEPCounter.count_reg1 = 0xFFFFFFFF;

/* Set increment value */
IEPCounter.global_cfg_reg_bit.default_inc = 4;

/* Enable counter */
IEPCounter.global_cfg_reg_bit.cnt_enable = 0x1;

}

My sample code is just to read the counter reg of IEP.

#if defined(PRU0_0)
g_pHSIO->SysInfo.CycleTime_PRU0_0 = IEPCounter.count_reg0;
#else
g_pHSIO->SysInfo.CycleTime_PRU2_1 = IEPCounter.count_reg0;
#endif

As you can see from below 2 pics. The number between the 2 regs have a big gap here.

Could you help to check why this happened?

Eric