DRA829V: [EP2000] Server, client IPC communication issue.

satyanandam gadde

Part Number: DRA829V

Tool/software:

Hello Expert,

I have built SDK9.2 version software for Ethfw and Vision apps for MCU2_0 (server) MCU2_1 (client),

case 1 : binaries from Ethfw build for MCU2_0 and MCU2_1 are working fine and able to communication through IPC and Ethernet TX and Rx are working on both Client and Server.

Case2 : MCU2_0 binary is from vision apps (platform build ) and MCU2_1 is from Ethfw (app_remoteconfig_client) here IPC handshake is not working to create virtual instances, could you please let us know what could be the issue? are these compatible with memory layouts?

Thanks and Regards,

Satya.

9 months ago

0 Doredla Sudheer Kumar 9 months ago

TI__Guru 65270 points

Hi,

satyanandam gadde said:
Case2 : MCU2_0 binary is from vision apps (platform build ) and MCU2_1 is from Ethfw (app_remoteconfig_client) here IPC handshake is not working to create virtual instances, could you please let us know what could be the issue? are these compatible with memory layouts?

If you are using vision-apps from TI SDK, IPC communication should work as expected.

But, Share memory communication via Inter-core Ethernet communication will not because the Inter-core communication address in ETHFW is different from one using with Vision-apps.
Please refer to ETHFW Linker file and Vision-apps Linker files for more details.

Best Regards,
Sudheer

0 satyanandam gadde 8 months ago in reply to Doredla Sudheer Kumar

Prodigy 110 points

Hi Sudheer,

We are integrating the MAIN2_0 Ethfw to our own repository at that time i can see all ports are up but having issue creating virtual ports on MAIN2_1 core because of IPC Handshake issue.

MAIN2_0 : Ethfw libriaries to our own repo (which is having simple dummy application)

MAIN2_1 : build from SDK directly

But if Server is sending IPC command messages multiple times client able to receive some of the packets, so what could be the issue with IPC how to resolve inconsistency of IPC communication between MAIN2_0 and MAIN2_1 ?

Regards,

Satya.

0 Doredla Sudheer Kumar 8 months ago in reply to satyanandam gadde

TI__Guru 65270 points

Hi,

satyanandam gadde said:
But if Server is sending IPC command messages multiple times client able to receive some of the packets, so what could be the issue with IPC how to resolve inconsistency of IPC communication between MAIN2_0 and MAIN2_1 ?

Have you confirmed memory mapping of client and Server is same as TI SDK?

Can you please share the memory map file of server & client.

Best Regards,
Sudheer

0 satyanandam gadde 8 months ago in reply to Doredla Sudheer Kumar

Prodigy 110 points

Hi Sudheer,

Please find the attached files for

Server Memmap files

Fullscreen 4375.linker_r5_freertos.txt Download

#include "memory_map_defines.inc"

#define __VECS                  MCU_R5F_TCMA_VECS
#define __BOOT                  MCU_R5F_TCMA
#define __CORE_IPC_DATA         MCU2_0_IPC_DATA
#define __CORE_EXT_DATA_BASE    MCU2_0_EXT_DATA_BASE
#define __CORE_EXT_DATA         MCU2_0_EXT_DATA
#define __CORE_R5F_MEM_TEXT     MCU2_0_MEM_TEXT
#define __CORE_R5F_MEM_DATA     MCU2_0_MEM_DATA
#define __CORE_DDR_SPACE        MCU2_0_DDR_SPACE

#include "linker_r5f_freertos_common.inc"

Fullscreen linker_r5f_freertos_common.txt Download

/*=========================*/
/*     Linker Settings     */
/*=========================*/

--retain="*(.bootCode)"
--retain="*(.startupCode)"
--retain="*(.startupData)"
--retain="*(.irqStack)"
--retain="*(.fiqStack)"
--retain="*(.abortStack)"
--retain="*(.undStack)"
--retain="*(.svcStack)"

--fill_value=0
--stack_size=0x2000
--heap_size=0x1000
--entry_point=_freertosresetvectors

-stack  0x4000  /* SOFTWARE STACK SIZE */
-heap   0x8000  /* HEAP AREA SIZE      */

/*-------------------------------------------*/
/*       Stack Sizes for various modes       */
/*-------------------------------------------*/
__IRQ_STACK_SIZE   = 0x1000;
__FIQ_STACK_SIZE   = 0x0100;
__ABORT_STACK_SIZE = 0x0100;
__UND_STACK_SIZE   = 0x0100;
__SVC_STACK_SIZE   = 0x0100;

/*--------------------------------------------------------------------------*/
/*                               Memory Map                                 */
/*--------------------------------------------------------------------------*/
MEMORY
{
    /*=================== MCU R5F TCM Local View ======================*/
    MCU_R5F_TCMA_VECS       (X) : ORIGIN = 0x00000000 LENGTH = 0x00000100
    MCU_R5F_TCMA            (X) : ORIGIN = 0x00000100 LENGTH = 0x00007F00
    MCU_R5F_TCMB_VECS       (X) : ORIGIN = 0x41010000 LENGTH = 0x00000040
    MCU_R5F_TCMB            (X) : ORIGIN = 0x41010040 LENGTH = 0x00007FC0

    /*==================== MCU R5F TCM SOC View =======================*/
    /*---------------------- MAIN R5FSS0 CORE0 ------------------------*/
    MCU2_R5F0_ATCM_RSVD  (RWIX) : ORIGIN = 0x05C00000 LENGTH = 0x00000040
    MCU2_R5F0_ATCM       (RWIX) : ORIGIN = 0x05C00040 LENGTH = 0x00007FC0
    MCU2_R5F0_BTCM_RSVD  (RWIX) : ORIGIN = 0x05C10000 LENGTH = 0x00000040
    MCU2_R5F0_BTCM       (RWIX) : ORIGIN = 0x05C10040 LENGTH = 0x00007FC0

    /*===================== MCU MSRAM Locations =======================*/
    OCMC_RAM_BOARD_CFG   (RWIX) : ORIGIN = 0x41C80000 LENGTH = 0x00002000
    OCMC_RAM             (RWIX) : ORIGIN = 0x41C82000 LENGTH = 0x0007DB00
    OCMC_RAM_X509_HEADER (RWIX) : ORIGIN = 0x41CFFB00 LENGTH = 0x00000500

    /*=================== COMPUTE_CLUSTER0_MSMC_SRAM ==================*/
    /*---------- J721E Reserved Memory for ARM Trusted Firmware -------*/
    MSMC3_ARM_FW         (RWIX) : ORIGIN = 0x70000000 LENGTH = 0x00020000   /* 128KB       */
    /*-----------------------------------------------------------------*/
    MSMC3                (RWIX) : ORIGIN = 0x70020000 LENGTH = 0x007D0000   /* 8MB - 192KB */
    /*------------- J721E Reserved Memory for DMSC Firmware -----------*/
    MSMC3_DMSC_FW        (RWIX) : ORIGIN = 0x707F0000 LENGTH = 0x00010000   /* 64KB        */

    /*===================== J721E DDR Locations =======================*/
    /* DDR Memory Map is included from memory_map_ddr.cmd -------------*/
}

/*--------------------------------------------------------------*/
/*                     Section Configuration                    */
/*--------------------------------------------------------------*/
SECTIONS
{
    .freertosrstvectors : {} palign(8)      > __VECS
    
    .bootCode           : {} palign(8)      > __BOOT
    .startupCode        : {} palign(8)      > __BOOT
    .startupData        : {} palign(8)      > __BOOT, type = NOINIT
    GROUP 
    {
        .text.hwi       : palign(8)
        .text.cache     : palign(8)
        .text.mpu       : palign(8)
        .text.boot      : palign(8)
    }                                       > __BOOT

    .text               : {} palign(8)      > __CORE_DDR_SPACE
    .const              : {} palign(8)      > __CORE_DDR_SPACE
    .rodata             : {} palign(8)      > __CORE_DDR_SPACE
    .cinit              : {} palign(8)      > __CORE_DDR_SPACE
    .bss                : {} align(4)       > __CORE_DDR_SPACE
    .far                : {} align(4)       > __CORE_DDR_SPACE
    .data               : {} palign(128)    > __CORE_DDR_SPACE
    .sysmem             : {}                > __CORE_DDR_SPACE
    .data_buffer        : {} palign(128)    > __CORE_DDR_SPACE
    .bss.devgroup       : {*(.bss.devgroup*)} align(4)         > __CORE_DDR_SPACE
    .const.devgroup     : {*(.const.devgroup*)} align(4)       > __CORE_DDR_SPACE
    .boardcfg_data      : {} align(4)       > __CORE_DDR_SPACE

    /* USB or any other LLD buffer for benchmarking */
    .benchmark_buffer (NOLOAD) {} align (8)     > __CORE_DDR_SPACE
    ipc_data_buffer (NOINIT) : {} palign(128)	> __CORE_DDR_SPACE
    .resource_table          : 
    {
        __RESOURCE_TABLE = .;
    }                                           > __CORE_EXT_DATA_BASE

    .tracebuf                : {} align(1024)   > __CORE_EXT_DATA

    .stack                   : {} align(4)      > __CORE_DDR_SPACE  (HIGH)

    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > __CORE_DDR_SPACE  (HIGH)
    RUN_START(__IRQ_STACK_START)
    RUN_END(__IRQ_STACK_END)

    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > __CORE_DDR_SPACE  (HIGH)
    RUN_START(__FIQ_STACK_START)
    RUN_END(__FIQ_STACK_END)

    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > __CORE_DDR_SPACE  (HIGH)
    RUN_START(__ABORT_STACK_START)
    RUN_END(__ABORT_STACK_END)

    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > __CORE_DDR_SPACE  (HIGH)
    RUN_START(__UND_STACK_START)
    RUN_END(__UND_STACK_END)

    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > __CORE_DDR_SPACE  (HIGH)
    RUN_START(__SVC_STACK_START)
    RUN_END(__SVC_STACK_END)

    .bss:ipc_vring_mem      (NOLOAD) : {} > SHARED_DDR_SPACE_START
}

Fullscreen memory_map_ddr.txt Download

/*============================*/
/*      DDR MEMORY MAP        */
/*============================*/

#include "memory_map_defines.inc"

MEMORY
{
    DDR0_RESERVED       (RWIX)  : ORIGIN = DDR0_RESERVED_START      LENGTH = DDR0_RESERVED_SIZE 
    /*---------------------------------- MAIN R5FSS0 CORE0 ------------------------------*/
    MCU2_0_IPC_DATA     (RWIX)	: ORIGIN = MCU2_0_IPC_DATA_BASE     LENGTH = IPC_DATA_SIZE
    MCU2_0_EXT_DATA     (RWIX)	: ORIGIN = MCU2_0_EXT_DATA_BASE     LENGTH = EXT_DATA_SIZE
    MCU2_0_R5F_MEM_TEXT (RWIX)	: ORIGIN = MCU2_0_MEM_TEXT_BASE     LENGTH = MEM_TEXT_SIZE
    MCU2_0_R5F_MEM_DATA (RWIX)	: ORIGIN = MCU2_0_MEM_DATA_BASE     LENGTH = MEM_DATA_SIZE
    MCU2_0_DDR_SPACE    (RWIX)	: ORIGIN = MCU2_0_DDR_SPACE_BASE    LENGTH = DDR_SPACE_SIZE
    /*---------------------------------- Shared Region ----------------------------------------*/
    SHARED_DDR_SPACE    (RWIX)	: ORIGIN = SHARED_DDR_SPACE_START  LENGTH = SHARED_DDR_SPACE_SIZE  
}

Fullscreen memory_map_defines.txt Download

#define DDR0_RESERVED_START     0x80000000
#define DDR0_RESERVED_SIZE      0x20000000 /* 512MB */

#define DDR0_ALLOCATED_START    0xA0000000 /* DDR0_RESERVED_START + DDR0_RESERVED_SIZE */

/*------------------------------------------------*/
/* Size of various Memory Locations for each core */ 
/*------------------------------------------------*/
#define IPC_DATA_SIZE   0x00100000 /*  1MB */
#define EXT_DATA_SIZE   0x00100000 /*  1MB */
#define MEM_TEXT_SIZE   0x00100000 /*  1MB */
#define MEM_DATA_SIZE   0x00100000 /*  1MB */
#define DDR_SPACE_SIZE  0x00C00000 /* 12MB */

#define CORE_TOTAL_SIZE 0x01000000 /* 16MB (IPC_DATA_SIZE + R5F_MEM_TEXT_SIZE + R5F_MEM_DATA_SIZE + DDR_SPACE_SIZE) */

/*-----------------------------*/
/* Start address for each core */ 
/*-----------------------------*/

#define MCU2_0_ALLOCATED_START   0xA2000000   /* 0xA2000000 */
#define RESV_ALLOCATED_START     0xA9000000   /* 0xA9000000  - Reserved */

#define SHARED_DDR_SPACE_START   0xAA000000   /* 0xAA000000 */
#define SHARED_DDR_SPACE_SIZE    0x02000000  /*  32MB */

/*--------------------------- MAIN R5FSS0 CORE0 -------------------------*/
#define MCU2_0_IPC_DATA_BASE     MCU2_0_ALLOCATED_START
#define MCU2_0_EXT_DATA_BASE     MCU2_0_IPC_DATA_BASE     + IPC_DATA_SIZE
#define MCU2_0_MEM_TEXT_BASE     MCU2_0_EXT_DATA_BASE     + EXT_DATA_SIZE
#define MCU2_0_MEM_DATA_BASE     MCU2_0_MEM_TEXT_BASE     + MEM_TEXT_SIZE
#define MCU2_0_DDR_SPACE_BASE    MCU2_0_MEM_DATA_BASE     + MEM_DATA_SIZE

0 satyanandam gadde 8 months ago in reply to satyanandam gadde

Prodigy 110 points

Hi Sudheer,

Above i attached Server linker files and client is same from SDK, app_remoteconfig_client of Ethfw. Let me know if anything is required.

Client linker files.

Fullscreen linker_freertos.txt Download

/* linker options */

--retain="*(.bootCode)"
--retain="*(.startupCode)"
--retain="*(.startupData)"
--retain="*(.irqStack)"
--retain="*(.fiqStack)"
--retain="*(.abortStack)"
--retain="*(.undStack)"
--retain="*(.svcStack)"

--fill_value=0
--stack_size=0x8000
--heap_size=0x10000
--entry_point=_freertosresetvectors

-stack  0x8000  /* SOFTWARE STACK SIZE */
-heap   0x10000 /* HEAP AREA SIZE      */

/*-------------------------------------------*/
/*       Stack Sizes for various modes       */
/*-------------------------------------------*/
__IRQ_STACK_SIZE   = 0x1000;
__FIQ_STACK_SIZE   = 0x0100;
__ABORT_STACK_SIZE = 0x0100;
__UND_STACK_SIZE   = 0x0100;
__SVC_STACK_SIZE   = 0x0100;

SECTIONS
{
    .freertosrstvectors : {} palign(8)      > _VEC
    
    .bootCode           : {} palign(8)      > R5F_TCMB0
    .startupCode        : {} palign(8)      > R5F_TCMB0
    .startupData        : {} palign(8)      > R5F_TCMB0, type = NOINIT
    GROUP 
    {
        .text.hwi       : palign(8)
        .text.cache     : palign(8)
        .text.mpu       : palign(8)
        .text.boot      : palign(8)
    }                                       > R5F_TCMB0

    .text_fast {
/* TODO: Commenting due to linking error reported for missing sections
         need to be removed when the enet-lld + lwip is integrated

        *(.text:EnetDma_retrieveRxPktQ*)
        *(.text:EnetDma_retrieveTxPktQ*)
        *(.text:EnetUdma_ringDequeue*)
        *(.text:EnetUdma_ringEnqueue*)
        *(.text:EnetUdma_submitPkts*)
        *(.text:EnetDma_submitRxPktQ*)
        *(.text:EnetDma_submitTxPktQ*)
        *(.text:EnetQueue_append*)
        *(.text:EnetQueue_copyQ*)
        *(.text:EnetQueue_deq*)
        *(.text:EnetQueue_enq*)
        *(.text:EnetQueue_enqHead*)
        *(.text:EnetQueue_getQCount*)
        *(.text:EnetUtils_physToVirt*)
        *(.text:EnetUtils_virtToPhys*)
        *(.text:Udma_ringQueueRaw*)
        *(.text:Udma_ringDequeueRaw*)
        *(.text:Udma_virtToPhyFxn*)
*/
     }     > DDR_MCU2_1

    .text_rest{
       _text_rest_begin = .;
       *(.text)
       _text_rest_end = .;
    } palign(32)    >  DDR_MCU2_1

    .const              : {} palign(8)      > DDR_MCU2_1
    .rodata             : {} palign(8)      > DDR_MCU2_1
    .cinit              : {} palign(8)      > DDR_MCU2_1
    .pinit              : {} palign(8)      > R5F_TCMB0
    .bss                : {} align(4)       > DDR_MCU2_1
    .far                : {} align(4)       > DDR_MCU2_1
    .data               : {} palign(128)    > DDR_MCU2_1
    .sysmem             : {}                > DDR_MCU2_1
    .data_buffer        : {} palign(128)    > DDR_MCU2_1
    .bss.devgroup       : { *(.bss.devgroup*) } align(4)   > DDR_MCU2_1
    .const.devgroup     : { *(.const.devgroup*) } align(4) > DDR_MCU2_1
    .boardcfg_data      : {} align(4)       > DDR_MCU2_1

    ipc_data_buffer (NOINIT) : {} palign(128)   > DDR_MCU2_1
    .resource_table          :
    {
        __RESOURCE_TABLE = .;
    }                                           > DDR_MCU2_1_RESOURCE_TABLE

    intercore_eth_desc_mem (NOLOAD) : {} palign(128) > INTERCORE_ETH_DESC_MEM
    intercore_eth_data_mem (NOLOAD) : {} palign(128) > INTERCORE_ETH_DATA_MEM

    .tracebuf                : {} align(1024)   > DDR_MCU2_1

    .bss:ENET_DMA_DESC_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
    .bss:ENET_DMA_RING_MEMPOOL  (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
    .bss:ENET_DMA_PKT_MEMPOOL   (NOLOAD) {} ALIGN (128) > DDR_MCU2_1
    .bss:ENET_DMA_OBJ_MEM       (NOLOAD) {} ALIGN (128) > DDR_MCU2_1

    .bss:app_log_mem        (NOLOAD) : {} > APP_LOG_MEM
    .bss:ipc_vring_mem      (NOLOAD) : {} > IPC_VRING_MEM
    .bss:ddr_shared_mem     (NOLOAD) : {} > DDR_MCU2_1

    .stack                   : {} align(4)      > DDR_MCU2_1  (HIGH)

    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > DDR_MCU2_1  (HIGH)
    RUN_START(__IRQ_STACK_START)
    RUN_END(__IRQ_STACK_END)

    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > DDR_MCU2_1  (HIGH)
    RUN_START(__FIQ_STACK_START)
    RUN_END(__FIQ_STACK_END)

    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > DDR_MCU2_1  (HIGH)
    RUN_START(__ABORT_STACK_START)
    RUN_END(__ABORT_STACK_END)

    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > DDR_MCU2_1  (HIGH)
    RUN_START(__UND_STACK_START)
    RUN_END(__UND_STACK_END)

    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > DDR_MCU2_1  (HIGH)
    RUN_START(__SVC_STACK_START)
    RUN_END(__SVC_STACK_END)
}  /* end of SECTIONS */

Fullscreen linker_mem_map.txt Download

/*
 * This file is AUTO GENERATED by PyTI_PSDK_RTOS tool.
 * It is NOT recommended to manually edit this file
 */
/*
 *
 * Copyright (c) 2018 Texas Instruments Incorporated
 *
 * All rights reserved not granted herein.
 *
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 *
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 * license under copyrights and patents it now or hereafter owns or controls to make,
 * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
 * terms herein.  With respect to the foregoing patent license, such license is granted
 * solely to the extent that any such patent is necessary to Utilize the software alone.
 * The patent license shall not apply to any combinations which include this software,
 * other than combinations with devices manufactured by or for TI ("TI Devices").
 * No hardware patent is licensed hereunder.
 *
 * Redistributions must preserve existing copyright notices and reproduce this license
 * (including the above copyright notice and the disclaimer and (if applicable) source
 * code license limitations below) in the documentation and/or other materials provided
 * with the distribution
 *
 * Redistribution and use in binary form, without modification, are permitted provided
 * that the following conditions are met:
 *
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 * permitted with respect to any software provided in binary form.
 *
 *        any redistribution and use are licensed by TI for use only with TI Devices.
 *
 *        Nothing shall obligate TI to provide you with source code for the software
 * licensed and provided to you in object code.
 *
 * If software source code is provided to you, modification and redistribution of the
 * source code are permitted provided that the following conditions are met:
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 * works, are licensed by TI for use only with TI Devices.
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 */

MEMORY
{
    /* R5F_TCMA [ size 32.00 KB ] */
    _VEC                     (    X ) : ORIGIN = 0x00000000 , LENGTH = 0x00000040
    R5F_TCMA                 (    X ) : ORIGIN = 0x00000100 , LENGTH = 0x00007F00
    /* R5F_TCMB0 [ size 32.00 KB ] */
    R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
    /* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
    DDR_MCU2_1_IPC           ( RWIX ) : ORIGIN = 0xA3000000 , LENGTH = 0x00100000
    /* DDR for MCU2_1 for Linux resource table [ size 1024 B ] */
    DDR_MCU2_1_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA3100000 , LENGTH = 0x00000400
    /* DDR for MCU2_1 for code/data [ size 63.00 MB ] */
    DDR_MCU2_1               ( RWIX ) : ORIGIN = 0xA3100400 , LENGTH = 0x00EFFC00
    /* Memory for remote core logging [ size 256.00 KB ] */
    APP_LOG_MEM                       : ORIGIN = 0xB8000000 , LENGTH = 0x00040000
    /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 31.75 MB ] */
    TIOVX_OBJ_DESC_MEM                : ORIGIN = 0xB8040000 , LENGTH = 0x01FC0000
    /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
    IPC_VRING_MEM                     : ORIGIN = 0xAA000000 , LENGTH = 0x02000000
    /* Memory for shared memory buffers in DDR [ size 560.00 MB ] */
    DDR_SHARED_MEM                    : ORIGIN = 0xBC000000 , LENGTH = 0x23000000
    /* Inter-core ethernet shared desc queues. MUST be non-cached or cache-coherent [ size 2 MB ] */
    INTERCORE_ETH_DESC_MEM            : ORIGIN = 0xAC000000 , LENGTH = 0x00200000
    /* Inter-core ethernet shared data buffers. MUST be non-cached or cache-coherent [ size 30 MB ] */
    INTERCORE_ETH_DATA_MEM            : ORIGIN = 0xAC200000 , LENGTH = 0x01E00000
}

0 Doredla Sudheer Kumar 8 months ago in reply to satyanandam gadde

TI__Guru 65270 points

Hi,

IPC vring (IPC_VRING_MEM) memory using in MCU2_0 is different from MCU2_1.

MCU2_1 if it is as per TI SDK: 0XA4000000 - 8MB
MCU2_0 it was SHARED_DDR_SPACE_START 0xAA000000 /* 0xAA000000 */

Please make both same i.e. change in client side as similar to sever side and check once.

Best Regards,
Sudheer

0 satyanandam gadde 8 months ago in reply to Doredla Sudheer Kumar

Prodigy 110 points

Hi Sudheer,

Sorry for the late reply, i was on the leave so didn't give response back.

Even though if i am referencing linker files from SDK still IPC not working completely due to that virtual interfaces not created for MCU2_1.

Please find the scenarios below.

1. Mapped the required libs to another Repository for MCU2_0

2. Mapped the linker files from SDK, and server application reused in another repo and build is succeeded.

3. Client binary simply flashed from SDK (which was working fine with sdk server binary)

still IPC was not working completely so not able understand which library or files we missed, could you please let me know your feasible time to schedule the call and do live debug?

Regards,

satya.

0 Doredla Sudheer Kumar 8 months ago in reply to satyanandam gadde

TI__Guru 65270 points

Hi,

Doredla Sudheer Kumar said:

IPC vring (IPC_VRING_MEM) memory using in MCU2_0 is different from MCU2_1.

MCU2_1 if it is as per TI SDK: 0XA4000000 - 8MB
MCU2_0 it was SHARED_DDR_SPACE_START 0xAA000000 /* 0xAA000000 */

As informed the IPC VRING is different in MCU2_0 and MCU2_1.

Please make it both same in MCU2_0 and MCU2_1.

satyanandam gadde said:
1. Mapped the required libs to another Repository for MCU2_0

2. Mapped the linker files from SDK, and server application reused in another repo and build is succeeded.

Vision Apps has own build infra and linker files.
Please check the address mapped in TI SDK .map file and vision apps build binary .map file for comparison.

Best Regards,
Sudheer

0 satyanandam gadde 8 months ago in reply to Doredla Sudheer Kumar

Prodigy 110 points

Hi Sudheer,

May be we are in different understanding can we have short discussion to align the issue ? if yes please let me know your feasible time to schedule the call.

Regards,

Satya.

0 Doredla Sudheer Kumar 8 months ago in reply to satyanandam gadde

TI__Guru 65270 points

Hi,

satyanandam gadde said:
May be we are in different understanding can we have short discussion to align the issue ? if yes please let me know your feasible time to schedule the call.

Please block 30Mins calendar at 4PM IST.

If you are changing the linker file of MCU2_0 from TI SDK mapped addresses then you need to make similar changes in MCU2_1 client as well.

Best Regards,
Sudheer

+1 Doredla Sudheer Kumar 8 months ago in reply to Doredla Sudheer Kumar

TI__Guru 65270 points

Hi All,

Updates from today's debug call.

Aptiv using custom build environment for Server, which is using different mpu config for memory regions definitions and properties.
As mpu config is different at client and server the IPC communication is not successful.
Suggested the mpu config to be included in custom build environment as in ETHFW.

After integrating the mpu config as in ETHFW the communication between client and server working as expected.

Best Regards,
Sudheer

Processors

Processors forum

DRA829V: [EP2000] Server, client IPC communication issue.