AM6421: MDIO signals for CPSW port in RMII

Hi,

I am currently out of the office and will return the second week of January.

Since you are using the MCU plus SDK, which processor are you planning to use the PRU ethernet port?

Best Regards,

Schuyler

Hi

 It is AM6421

Hi Schuyler Patton,

              Can you please kindly update.

Hi, 

Within the AM6421 are two different cores (A53-Linux, R5 FreeRTOS) that could processor the network traffic. Which core is the customer trying to use for network traffic? Could you please describe how the customer wants traffic to flow?

Best Regards,

Schuyler

Hi Schuyler Patton,

     We are using A53-Linux core for network traffic. It is interfaced to CPSW PORT as RMII interface between SOC and DP83822 PHY.

Looks like you need more information for clarity. So to detail out we need 3 ports for our project.

          TWO are used for industrial communication for EtherCAT in MII mode.

           ONE Port is used as CPSW Linux network port.

This we would love to have it as RGMII however due to constrains we had configured in HW as RMII.  This is where we need your support. We are having a challenge assigning MDIO port to RMII due to clash in pin assignment between MII and RMII. We need to use MII in MCU (R5F) domain where as RMII(linux) will be in A53 domain.

We have issue with driver programming Linux network port as MDIO and IOset are not inline in the HW. We would like to have clarity from you, how to use MDIO and IOset from different Groups. 

Thank You

Hi,

I am attaching a DTSI file generated by sysconfig that I did based on what you described. I didn't see mention of a second MDIO interface. This would be required if you are using a cpsw interface and a ICSSG interface. Is this correct?

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/cpsw_5F00_rmii_5F00_icssg_5F00_mdio_5F00_example.dtsi

Best Regards,

Schuyler

Hi Schuyler Patton,

   IO set provide in DTS file are different from the custom board we have. Since HW boards are already made, we are looking for solution for RMII lines that are details in the Schematic provided earlier.  We need your support for RMII driver that can be use MDIO line PRG0_MDIO0_MDC(P3) and PRG0_MDIO0_MDIO (P2) as in the Schematic. Appreciate if you could also provide link to any known working RMII driver on Linux.

Thank You.

Hi Schuyler Patton

   Any update. We appreciate early response. Customer is waiting for the product delivery.

Thank You

Hi,

I apologize as I may not be following what you are trying to tell me. If I am understanding the board design, is there only 1 MDIO interface designed on the board? This is the only MDIO interface that is mentioned in this post.

The typical design of the MDIO interface selected (Pins P3 and P2) is for ICSSG ports only. This is how it is configured on the TI EVMs.

I am not picking up yet in the problem description how the interfaces are divided between the processing cores (A53 or R5). If I understand the use case the CPSW will be running Linux. The question I have is if the R5 running an RTOS will be used to run the Industrial ports for EtherCAT?

If the R5s are intended to run ICCSG ports for the EtherCAT then it will then a separate MDIO interface will needed. One MDIO interface cannot be used to support the CPSW port running Linux and the R5 running an RTOS. 

Linux has the RMII driver support already. 

Best Regards,

Schuyler

Hi Schuyler,

We are using AM6421 with SDK

   1)  Processor SDK Linux for AM64x Version: 09.02.01.10 for A53

   2) ind_comms_sdk_am64x_09_02_00_15  for R5F.

   For your understanding of our use cases. Below are the details:

 1) We are using 2 ICSSG ports on PRG1 for 2 Industrial Ports, which are used for Ethercat, Ethernet/IP, Profinet-IRT.

       For this we are using PRG1_MDIO0_MDC(Y6) and PRG1_MDIO0_MDIO(AA6) as MDIO port.

       We are using this in R5F MCU  domain with FreeRtos.

      We do not have any issue in using this.

  Below is the schematic design

2) We are using 1 port on PRG0 for CPSW in A53 Main Domain with Linux OS.

     This port as RMII mode.

   For this hardware  has configured as PRG0_MDIO0_MDC(P3) and PRG0_MDIO0_MDIO(P2) as MDIO port.

  Below is the schematic design

We need  your support to enable RMII driver on Linux using the above MDIO bus (P3/P2)

Hi,

Since Linux and FreeRTOS is in use there will have to be two separate MDIO busses used. The P3/P2 pins cannot be shared with the CPSW if the RTOS on the R5 owns them. The R5 will have to own the P3/P2 pins since this is part of the PRU signal set. Linux will have to use the MDIO on pins R2/P5.

The sample DTSI file above is what will have to used. 

For example the CPSW running on Linux would use this MDIO:

/* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
/* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */

Best Regards,

Schuyler

Hi,

  Kindly note that from the schematic already attached for your reference do not use P2/P3 for Industrial MII configured ports.

Schuyler Said:

  "Since Linux and FreeRTOS is in use there will have to be two separate MDIO busses used. The P3/P2 pins cannot be shared with the CPSW if the RTOS on the R5 owns them." 

   << Please note the HW is already made and the schematic is shared. As per the schematic P3/P2 is used only by CPSW. >>

Schuyler Said:

"The R5 will have to own the P3/P2 pins since this is part of the PRU signal set. Linux will have to use the MDIO on pins R2/P5."

  << Since HW is already made can you please suggest a way to use P3/P2 for CPSW. This will help us to avoid scrap all the HW boards manufactured "

Thank You

Hi,

          Any update on our above reply for the clarification asked.

           We appreciate your quick reply.

Thank you