PROCESSOR-SDK-AM64X: AM64X How to solve the data consistency problem between R5 and A53 shared memory

Jeper zhu

Tool/software:

Dear developer

I want to do shared memory between R5 and A53. For example, I do it at 0xb000 0000, A53 maps 0xb000 0000 to the virtual address through MMAP, A53(running linux) writes data to the virtual address, and then R5 reads data from 0xb000 0000. But the testing show that A53 data will enter the cache, resulting in R5 cannot read. I don't know how to solve the consistency problem? Please offer some suggestions.

Regards,

Jeper

15 days ago

0 Nick Saulnier 4 days ago

TI__Guru* 89075 points

Hello Jeper,

Please start by taking a look at our zerocopy example:
https://git.ti.com/cgit/rpmsg/rpmsg_char_zerocopy/

You can find additional updates on that project in this Sept 11 response:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1410313/am6442-communication-latency-issues-between-a53-and-r5-in-a-linux-rt-system/5407807#5407807

For other multicore design concepts (e.g., how to ensure that memory maps align between Linux and R5F), refer to the AM64x academy's Multicore module:
https://dev.ti.com/tirex/explore/node?node=A__AJa64F6ctzZNbb.TYx4mCA__AM64-ACADEMY__WI1KRXP__LATEST

Regards,

Nick

0 Jeper zhu 4 days ago in reply to Nick Saulnier

Prodigy 10 points

Thanks for suggestions. Wish you good luck in the New Year.

Processors

Processors forum

PROCESSOR-SDK-AM64X: AM64X How to solve the data consistency problem between R5 and A53 shared memory