Urgent help needed on layout for AM3505!

Their recommendation of locating the PHY within 6 inches of the MAC may not guarantee the system meets all timing requirements.  We recommend customers verify the timing budget for each signal path based on data sheet parameters from both devices and PCB delay characteristics.

You can assume both PHY and MAC see the clock transitions at the same time if the source is place midway between the PHY and MAC as described below.  If this were the case, you can calculate the setup time margin of each RMII signal by subtracting the respective clock to output delay characteristic and PCB trace delay from the clock cycle period.  If the result is greater than the respective input setup requirement, you still have setup margin.  You can calculate the hold time margin of each RMII signal by add the respective clock to output delay characteristic and PCB trace delay.  If the result is greater than the respective input clock to hold time requirement, you still have hold margin.

If the clock source is not placed midway between the PHY and MAC, you can do similar calculations after making adjustments that account for the clock arriving at one device before the other.

I do not see any issue with the other recommendations.

Regards,

Paul

Thanks Paul,
In addition, please see below.

· What would be a safe margin for an industrial operation temperature range? It looks like the margin without propagation delay is 2 to 3 nsec. Would 20 % of this used for PCB trace delay be adequate?

· TI recommends in its AM35x Schematic Checklist to use the LAN8710 (also used in the AM35x EVM board from LogicPD) instead of the RMII-only LAN8720 chip. At first parsing, the RMII timing looks very similar – is the problem in the management layer?

Thanks!

Amy

PCB board delay is about 150-180ps per inch and does not vary much with temperature.  2-3ns is about 15 inches of PCB trace.  Which confirms the 6 inch recommendation from SMSC is conservative.

The primary reason to switch to the SMSC LAN8720 is to allow it to operate in REF_CLK out mode which allows it to source the 50MHZ RMII reference clock to the MAC from the internal crystal oscillator.  This saves the cost difference between an external 50MHz LVCMOS clock source vs a 50 MHZ crystal.  However, the SMSC LAN8720 operating in REF_CLK out mode has two timing parameters that do not meet the RMII specification.

The timing parameter t_ohold, which is the minimum delay time for the RXD[1:0], RXER, and CRS_DV outputs to transition after the rising edge of REFCLKO, is specified as 1.4ns in the Revision 1.3 data sheet.  The RMII specification defines the minimum input hold time as 2ns.  The AM35xx data sheet also has a 2ns minimum hold time requirement for these signals.  This would require the RXD[1:0], RXER, CRS_DV signal traces to be about  4 inches longer than the REFCLK signal to meet the RMII specification. 

The timing parameter t_su, which is the minimum setup time for the TXD[1:0] and TXEN inputs to transition before the rising edge of REFCLKO, is specified as 7.0ns in the Revision 1.3 data sheet.  The RMII specification defines the minimum input setup time as 4ns.  The AM35xx data sheet has a 13ns maximum delay characteristic for the TXD[1:0] and TXEN outputs which would be compatible with the RMII specified minimum setup time requirement of 4ns, but is not compatible with the LAN8720 specified minimum setup time requirement of 7ns.  This does not provide any margin for PCB trace delay.

You should be able to use the LAN8720 if configured to operate in REF_CLK in mode.

Regards,

Paul