Tool/software:
Hi,
My customer has some questions about GPMC Read Access. Could you answer their questions below ?
1. GPMC_BEn at 8-bit read access with 16-bit data bus width
At 8-bit read access, the customer expected GPMC_BE[1:0]n to be "10" or "01", but the output was "00" when the waveform was observed.
At 8-bit write access, this was “10” or ”01”.
Are these behavior correct ? Could you tell them where the datasheet or TRM is written about that ?
2. 32-bit read access with 16-bit data bus width
At single 32-bit read access, they thought that 16-bit read access would be performed twice, but GPMC_CSn was asserted only once when I observed the waveform, and it behaves like a burst read. (Reading the GPMC_AD value twice with CS asserted.)
They can’t find the description in the datasheet or TRM about such like this behavior.
On the other hand, for 32-bit write access, there are two 16-bit accesses.
Could you share the timing waveform of the 32-bit read access when the bus width is 16 bits?
<GPMC Configurations>
DEVICETYPE:NOR device
DEVICESIZE:16bit
MUXADDDATA:address and data-multiplexed attached device
READMULTIPLE:Single access
READTYPE:Read synchronous
WRITEMULTIPLE:Single access
WRITETYPE:Write synchronous
Thanks and regards,
Hideaki
