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2 C6672 on a single embedded module design

Wenjun Huang85261
Prodigy 150 points
Other Parts Discussed in Thread: CDCE62005, UCD9222, UCD7242

I am designing 2 C6672 on one embedded module (1 PCB) by reference designing from C6678EVM. What should be taken note of when referencing design from the C6678 EVM?

Below is what I believe to be the modification.

a. Use 4 CDCE62005s to provide clocking for the 2 C6672. Is there a better way to provide clocking to the 2 C6672 such as using 2 CDCE62005s and 1 clock output to 2 C6672?

b. For each c6672, the DDR3 SDRAM, NAND Flash, NOR SPI flash, I2C EEPROM shoud be separate and not shared by the 2? DDR3, NAND, NOR SPI cannot be shared as it is point to point interface? I2C although it allows for multi-master mode but for simplificity uses separate for the 2 C6672.

c. How to do power-up sequencing (which includes power, clock and device initialization)? 1 C6672 boot up first with the main program logic whereas the second C6672 is used for offloading the main C6672 in term of image processing algo. Is the power up sequencing same regardless of the number of C6672 used?

  • 0
    TI__Mastermind 42545 points

    a.  You should look at the clocking solution specific to your design.  The EVM is designed with the flexibility to provide different clock frequencies for each of the clock inputs.  This may be overkill for you application.  For example, if you are using the same frequency for your SERDES reference clocks you may be able to use the clock generator to create the clock and a clock distribution part to distribute multiple copies.  In addition you may not be using one or more of the SERDES interfaces which would eliminate the need to drive the reference frequency of that interface.  This could reduce the number of clocks you need to generate.

    b. The DDR3 SDRAM, NAND flash and NOR SPI flash cannot be shared between the two devices.  The I2C EEPROM can be shared.  Again you need to look at your specific application.  If you are booting from I2C and NAND you may not need the NOR SPI memory.  You may be able to boot one of the processors from NAND or NOR SPI and use that as a master to boot the second processor across SRIO.  Regardless you will need either I2C or NOR SPI memory to boot based on the present Errata document.

    c. The power sequencing is the same whether you have one or two devices.  If your application is only using one of the processors for part of the time then both processors should be powered and booted before putting the second processor into a hibernation mode to save power.  Note that each processor must have it's own core power supply since each may have a different voltage level requirement for the core.  The fixed 1V supply (CVDD1), the 1.8V and 1.5V supplies can be common between the two processors but be sure to scale these supplies to support the current requirements for both parts. 

     

  • 0 in reply to Bill Taboada
    Prodigy 150 points

    Thanks for the info. 

    I did not know the presence of clock distributor before your recommendation. If I am using 100MHz for 3 of my clock per C6672. It means I can use a clock generator CDCE62005 to generate the 100MHz and a clock distributor to output six 100MHz to the two C6672s.

    I intend to reference design from the C6678 EVM board as far as possible, which is to boot first from I2C EEPROM, either POST program (50h) or IBL (Intermediate Boot Loader) (51h). The IBL will be used to boot from NAND or NOR flash depending on DIP switch settings.

    I believe I can use 1 UCD9222 and 1 UCD7242 to generate the two CVDDs for the two C6672s since the C6678 EVM uses UCD9222 and UCD7242 to generate CVDD and the CVDD1 (fixed 1V). For generating the CVDD1, I can use a normal regulator solution.