Tool/software:
I noticed in ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/drv/gpio/soc/j721e/GPIO_soc.c that the code seems to be written for 16 GPIO pins per GPIO bank. Look at lines 470 and 511 around the function GPIO_socConfigIntrPath().The J721e has 32 GPIO pins per GPIO bank.
Looking at ti-processor-sdk-rtos-j721e-evm-10_00_00_05/pdk_jacinto_10_00_00_27/packages/ti/csl/csl_gpioAux.h, there are some comments that claim there are 16 GPIO signals per bank. At the same time, if you look at the code for CSL_GPIO_getInputData(), you can see that the function is clearly written for 32 GPIO pins for bank.
What is going on here? Am I misunderstanding something?
