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AM623: QSPI flash write rate

Part Number: AM623


Tool/software:

Hi, TI expert! 

I have a development environment for am6234, with our own evaluation board.

The software SDK version is PROCESSOR-SDK-LINUX-RT-AM62X-08.06.00.42.

Our am6234 chip is connected to a flash with the model number w25q128(page size 256 Bytes, erase size 4 KiB, total 16 MiB), and its schematic diagram is as follows:

The corresponding device tree configuration is as follows:

	fss: bus@fc00000 {
		compatible = "simple-bus";
		reg = <0x00 0x0fc00000 0x00 0x70000>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ospi0: spi@fc40000 {
			compatible = "ti,am654-ospi", "cdns,qspi-nor";
			reg = <0x00 0x0fc40000 0x00 0x100>,
			      <0x05 0x00000000 0x01 0x00000000>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x0>;
			clocks = <&k3_clks 75 7>;
			assigned-clocks = <&k3_clks 75 7>;
			assigned-clock-parents = <&k3_clks 75 8>;
			assigned-clock-rates = <166666666>;
			power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};
	
&main_pmx0 {
	ospi0_pins_default: ospi0-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
		>;
	};
};

&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;

	spi_nor_flash: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;
		cdns,phy-mode;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ospi.u-boot";
				reg = <0 0x400000>; // 4MB
			};
		};
	};
};

Meanwhile, the configuration of the kernel is as follows:

CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set

I have two questions:

1.What is the maximum configurable value for SPI max frequency? Is there any limit on the maximum speed?

https://software-dl.ti.com/processor-sdk-linux-rt/esd/AM62X/10_01_10_04/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/QSPI.html

When I configure SPI max frequency to 52000000Hz, there is an error prompt:

When I configured SPI max frequency to 4166666 Hz, there were no errors:

2.How to improve the write speed of SPI flash?

When the SPI max frequency is configured to 4166666hz, writing 4MB of data to SPI flash takes 28.0269 seconds, as follows:

root@AM62x:~# dmesg |grep spi
[    0.746496] cadence-qspi fc40000.spi: registered master spi5
[    0.746533] spi spi5.0: setup: ignoring unsupported mode bits 200
[    0.746542] spi spi5.0: setup mode 0, 8 bits/w, 4166666 Hz max --> 0
[    0.746860] spi-nor spi5.0: w25q128 (16384 Kbytes)
[    0.746893] 1 fixed-partitions partitions found on MTD device fc40000.spi.0
[    0.746899] Creating 1 MTD partitions on "fc40000.spi.0":
[    0.746905] 0x000000000000-0x000000400000 : "ospi.u-boot"
[    0.748442] cadence-qspi fc40000.spi: registered child spi5.0
[    0.749758] omap2_mcspi 4b00000.spi: registered master spi0
[    0.750860] omap2_mcspi 20100000.spi: registered master spi2
root@AM62x:~#
root@AM62x:~# cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00400000 00010000 "ospi.u-boot"
root@AM62x:~#
root@AM62x:~#
root@AM62x:~# dd if=/dev/urandom of=/dev/mtdblock0 bs=64K count=64
64+0 records in
64+0 records out
4194304 bytes (4.2 MB, 4.0 MiB) copied, 28.1373 s, 149 kB/s
root@AM62x:~# dd if=/dev/urandom of=/dev/mtdblock0 bs=1M count=4
4+0 records in
4+0 records out
4194304 bytes (4.2 MB, 4.0 MiB) copied, 28.0269 s, 150 kB/s
root@AM62x:~#
root@AM62x:~#
root@AM62x:~#
root@AM62x:~# dd if=/dev/urandom of=test.bin bs=1M count=4
4+0 records in
4+0 records out
4194304 bytes (4.2 MB, 4.0 MiB) copied, 0.0695056 s, 60.3 MB/s
root@AM62x:~#
root@AM62x:~# dd if=test.bin of=/dev/mtdblock0 bs=1M count=4
4+0 records in
4+0 records out
4194304 bytes (4.2 MB, 4.0 MiB) copied, 28.0232 s, 150 kB/s

When the SPI max frequency is configured to 25000000hz, writing 4MB of data to SPI flash takes 27.1244 seconds, as follows:

root@AM62x:~# dd if=/dev/urandom of=/dev/mtdblock0 bs=1M count=4
4+0 records in
4+0 records out
4194304 bytes (4.2 MB, 4.0 MiB) copied, 27.1244 s, 155 kB/s

It seems that the increase in clock frequency has no effect on the speed of writing flash

Regards,

Li

  • Hi Li,

    The software SDK version is PROCESSOR-SDK-LINUX-RT-AM62X-08.06.00.42.

    You should be using the recently-released SDK v10.1. SDK v8.6 you have is two years old and no longer supported. There've been many improvements across the entire software stack you would want to take advantage of (security, performance, bug fixes).

    https://www.ti.com/tool/download/PROCESSOR-SDK-LINUX-AM62X/10.01.10.04

    1.What is the maximum configurable value for SPI max frequency? Is there any limit on the maximum speed?

    From an OSPI/QSPI IP point of view, there are two fundamental operating modes, which determine the max. speed, as follows:

    1. Tap Mode: This mode of operation can go up to 50 MHz maximum, relatively straightforward to setup.

    2. PHY Mode: This mode of operation can go up to 166 MHz, but cannot go below 100 MHz (due to how the DLL functions). This mode also involves doing some data training during each initial power on setup. 

    PHY mode should be fully supported for OSPI NOR Flashes with your SDK version, but not for anything else. If you move to SDK v10.x you get PHY mode support also for QSPI NAND Flashes, but still not QSPI NOR which is what you have with w25q128 I think.

    Without SW support, you are limited to "Tap Mode", means 50MHz max. frequency. In order to get to this the device clock tree need to be able to divide the functional clock input frequency into the OSPI peripheral module cleanly (integer divider) down to 50MHz, otherwise things will get approximated, and you don't actually see a difference in effective speed even you change the DTS frequency by manipulating spi-max-frequency.

    By default the module clock input frequency is 166MHz. If you want to be able to get to 50MHz SPI frequency you need to configure the module clock input frequency to 200MHz, as 200MHz can be cleanly divided down to 50MHz (/4).

    For this, try changing assigned-clock-rates = <166666666> to assigned-clock-rates = <200000000> in the device tree, and then configure spi-max-frequency to 50MHz.

    Regards, Andreas

  • Hi Andreas

    You should be using the recently-released SDK v10.1. SDK v8.6 you have is two years old and no longer supported. There've been many improvements across the entire software stack you would want to take advantage of (security, performance, bug fixes).

    Is this issue relevant to the SDK version? Many customers‘ AM62 projects started to develop in 2022, and currently their products are in MP, updating the SDK is impractical, should we have some long-term maintained SDK releases? Do we have plans for long-term maintenance of a version of the SDK? SDK10.1 is okay? Customers do not always upgrade their software with our SDK release updates.

    Regards

    Ethan

  • Hi Ethan,

    Is this issue relevant to the SDK version?

    You should be able to use the steps I shown to configure SDK v8.6 to run QSPI NOR operation at 50MHz. As far as I know we don't have anything faster beyond that at the moment for QSPI NOR (only for QSPI NAND), even on the latest v10.1 SDK. However there are some internal requirements regarding this (e.g., SITREQ-1102) that are used as part of the SDK v11.0 planning, but I don't see any committed work on this yet.

    Many customers‘ AM62 projects started to develop in 2022, and currently their products are in MP, updating the SDK is impractica

    Understood.

    should we have some long-term maintained SDK releases? Do we have plans for long-term maintenance of a version of the SDK? SDK10.1 is okay?

    SDK v10.1 is supposed to be the last release of the SDK v10.x series, just as v8.6 is the last release of the 2-year old v8.x series. We usually don't go back to update older SDK releases series based on fixes/improvements from newer SDK versions. It is considered customer responsibility to monitor new SDK releases, and backport applicable fixes as needed.

    There's a long-term maintenance aspect to this as well. All our SDK releases are based on long-term stable kernel releases, which are maintained by the community for a number of years, well beyond our SDK release date. For example in SDK v8.6 the Linux Kernel v5.10 is used, which is officially supported by the community with critical fixes until Dec 2026, see https://www.kernel.org/category/releases.html  What this means one can easily monitor/track the "stable" branches (https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/log/?h=linux-5.10.y) of those Kernels and merge changes back into the SDK v5.10 kernel for example without much effort. However this only applies to the Kernel, there are many more SW components in a given system of course.

    Regards, Andreas

  • However this only applies to the Kernel, there are many more SW components in a given system of course.

    So can SDK v10.1 be used as a long-term maintenance version?

  • You should be using the recently-released SDK v10.1. SDK v8.6 you have is two years old and no longer supported. There've been many improvements across the entire software stack you would want to take advantage of (security, performance, bug fixes).

    Is TI's support for the latest SDK v10.1 also two years?

  • Hi Li,

    Is TI's support for the latest SDK v10.1 also two years?

    Standard support is 1 year development (bug fixes, re-releases), and one year apps (mostly through E2E). Anything beyond that is "best effort".

    There are however plans in the SW roadmap to provide real long term support based on the CIP and Super LTS initiatives in the community. But this doesn't apply to v10.1.

    Regards, Andreas

  • For this, try changing assigned-clock-rates = <166666666> to assigned-clock-rates = <200000000> in the device tree, and then configure spi-max-frequency to 50MHz.

    I followed the method you suggested and there were errors after testing, as shown in the following picture:

  • I'm currently on international business travel working at a customer site and not able to look into this further; will comment once I'm back in the office next week.

    Regards, Andreas

  • Hello, has there been any new progress on this issue?

  • There are however plans in the SW roadmap to provide real long term support based on the CIP and Super LTS initiatives in the community. But this doesn't apply to v10.1.

    Does TI have a Super LTS plan for the following version of SDK?
    https://software-dl.ti.com/processor-sdk-linux-rt/esd/AM62X/09_02_01_10/exports/docs/devices/AM62X/linux/Release_Specific_Release_Notes.html

    further more,what versions of SDK does TI's Super LTS plan support?

  • Does TI have a Super LTS plan for the following version of SDK?
    https://software-dl.ti.com/processor-sdk-linux-rt/esd/AM62X/09_02_01_10/exports/docs/devices/AM62X/linux/Release_Specific_Release_Notes.html

    further more,what versions of SDK does TI's Super LTS plan support?

    We have some planning initiatives around this for future SDKs. While the details are still being discussed I'm pretty sure this is an SDK v11+ initiative, nothing that will apply to older SDKs like 9.x or even 10.x.

    I followed the method you suggested and there were errors after testing, as shown in the following picture

    Can you try the current SDK v10.1 to see if you can get this to work with your Flash. There've been many improvements in the drivers, so that's something you'd want to try first. Once you have something working we can always consider identifying and back-porting specific changes as needed.

    Regards, Andreas

  • We have some planning initiatives around this for future SDKs. While the details are still being discussed I'm pretty sure this is an SDK v11+ initiative, nothing that will apply to older SDKs like 9.x or even 10.x.

    Hello,Andreas

    The Civil Infrastructure Platform project have just announced to select the new 6.12 kernel as 5th SLTS (super long-term stable) kernel,We are planning a version upgrade and would like to confirm which version of SDK to choose as the long-term version.

    https://www.cip-project.org/blog/2025/01/13/kernel-6-12-will-have-10-years-support-via-cip-are-all-your-maintenance-problems-solved

    Will TI's next version be released in March this year? Is the next version SDK v10.2 or SDK v11+? Is the kernel version corresponding to SDK v11+ Linux 6.12?

    Regards, LI

  • Can you try the current SDK v10.1 to see if you can get this to work with your Flash. There've been many improvements in the drivers, so that's something you'd want to try first. Once you have something working we can always consider identifying and back-porting specific changes as needed.

    Testing in SDK v10.1 is also unsuccessful as the device ID cannot be recognized:

  • Is there any new progress on this issue?

    Can you try the current SDK v10.1 to see if you can get this to work with your Flash. There've been many improvements in the drivers, so that's something you'd want to try first. Once you have something working we can always consider identifying and back-porting specific changes as needed.