AM6442: Power Down Sequence Restrictions

Mari Tsunoda

Expert 5726 points

Part Number: AM6442
Other Parts Discussed in Thread: SK-AM64B, TPS65220

Tool/software:

Hi Team,

My customer has a question as below.

Is the shut down requirement the two points below?

VDDR_CORE must power down before VDD_CORE
VDDR_CORE potential must never exceed VDD_CORE+018V

So therefore, can power rails other than VDDR_CORE, VDDS_DDR, and VDDS_DDR_C can be powered down at the same time or after VDD_CORE?

By default, the power sequence of the TPS6521901, BUCK1(+0.75V) powers down 10ms after BUCK2(+3.3V/+1.8V).

However, my customer wants to supply BUCK1 to VDD_CORE, BUCK2 to VDDSHV(0~5) of the AM6442.

VDDSHV will power down after VDD_CORE, but is this ok?

Best regards,

Mari Tsunoda

8 months ago

0 Kallikuppa Sreenivasa 8 months ago

TI__Guru**** 192429 points

Hello Mari Tsunoda

Thank you for the query .

Let me review the inputs and comeback.

Regards,

Sreenivasa

0 Mari Tsunoda 8 months ago in reply to Kallikuppa Sreenivasa

TI__Expert 5726 points

Hi Sreenivasa,

Do you have any update on this?

Best regards,

Mari Tsunoda

0 Kallikuppa Sreenivasa 8 months ago in reply to Mari Tsunoda

TI__Guru**** 192429 points

Hello Mari Tsunoda

Thank you.

Please refer inputs from out device expert:

We have plans to update the next revision of the AM64x datasheet such that it allows the VDDSHV power rails to turn off as late as the last core supply, but we do not allow it to turn off after the last core supply.

Regards,

Sreenivasa

0 Jim Mrowca 8 months ago in reply to Kallikuppa Sreenivasa

Genius 4132 points

Sreenivasa: at least that should be errata -- or create one of your FAQs.

0 Kallikuppa Sreenivasa 8 months ago in reply to Jim Mrowca

TI__Guru**** 192429 points

Hello Jim,

Thank you and appreciate the inputs.

Inputs are noted. I will consult our device expert and take this forward.

Regards,

Sreenivasa

0 Kei Kuwahara 8 months ago in reply to Kallikuppa Sreenivasa

TI__Expert 7700 points

Hello Kallikuppa-san,

I am taking over Tsunoda-san's question.

Kallikuppa Sreenivasa said:
We have plans to update the next revision of the AM64x datasheet such that it allows the VDDSHV power rails to turn off as late as the last core supply, but we do not allow it to turn off after the last core supply.

For power-up sequence, VDDSHV power-up before VDD_CORE from the Figure 6-5 on the datasheet.
Is it still true?
Usually, power up and down sequences are symmetrical.

Is there any more changes regarding power sequence from the latest datasheet?

Best Regards,
Kei Kuwahara

0 Kallikuppa Sreenivasa 8 months ago in reply to Kei Kuwahara

TI__Guru**** 192429 points

Kei Kuwahara said:
For power-up sequence, VDDSHV power-up before VDD_CORE from the Figure 6-5 on the datasheet.
Is it still true?

This is inline with the power-up sequence

Kei Kuwahara said:
Usually, power up and down sequences are symmetrical.

Is there any more changes regarding power sequence from the latest datasheet?

The changes are based on customer queries and multiple architecture reviews.

I am not aware of any additional changes.

Regards,

Sreenivasa

0 Thomas Langhammer 8 months ago in reply to Kallikuppa Sreenivasa

Intellectual 580 points

Hi,

The SK-AM64B board from TI uses the (recommended) PMIC TPS6522053, but this PMIC ramps down VCORE supplies first and VDDSHV (3.3V) later in its power down sequence. This is documented in the PMIC data sheet and also in the schematics of the SK-AB64B. So if it is not allowed to ramp down VDDSHV after VCORE the recommended PMIC seems to violate this. Despite this, can the TPS6522053 be safely used in a AM6442 design?

Regards

Tom

0 Kallikuppa Sreenivasa 8 months ago in reply to Thomas Langhammer

TI__Guru**** 192429 points

Hello Tom,

The PMIC has been configured to support AM64x.

Kallikuppa Sreenivasa said:
Please refer inputs from out device expert:

We have plans to update the next revision of the AM64x datasheet such that it allows the VDDSHV power rails to turn off as late as the last core supply, but we do not allow it to turn off after the last core supply.

The change in sequence provides additional flexibility and this is based on internal discussion as well as custoer requests/queries.

Regards,

Sreenivasa

0 Thomas Langhammer 8 months ago in reply to Kallikuppa Sreenivasa

Intellectual 580 points

Hi,
I am referring to the data sheet of the recommended PMIC TPC6522053. It shows that the DVDD3V3 rail (green) is ramped down after the VDD_CORE rail (red):

However this does not match the requirement from your device expert:
"We have plans to update the next revision of the AM64x datasheet such that it allows the VDDSHV power rails to turn off as lateas the last core supply, but we do not allow it to turn off after the last core supply."

I also measured the PMIC voltages and can confirm that it ramps down the 3.3V VDDSHV after VCORE on the SK-AM64B board, so this is in line with the spec of the PMIC, but not compliant with the power down sequencing spec of the AM64x. So maybe there is an issue with the documentation?

Regards

Tom

0 Kallikuppa Sreenivasa 8 months ago in reply to Thomas Langhammer

TI__Guru**** 192429 points

Hello Tom,

Thank you for the inputs.

Please refer Figure 7-6. Power-Down Sequencing of the data sheet where the last supply allowed to fall in the sequence is the core voltage.

The Device experts comments are with respect to the AM64x data sheet.

I understand your concerns. Let me check with the power expert and update you.

Regards,

Sreenivasa

0 Kei Kuwahara 8 months ago in reply to Kallikuppa Sreenivasa

TI__Expert 7700 points

Hello Kllikuppa-san,

My customer is asking the exactly same question as Thomas asked.
It's just that the device they are planning to use is TPS6521901.

Have you heard anything back from the power expert?

Best Regards,
Kei Kuwahara

0 Kallikuppa Sreenivasa 8 months ago in reply to Kei Kuwahara

TI__Guru**** 192429 points

Hi All,

I marked to the power expert to support.

Regards,

Sreenivasa

0 Thomas Langhammer 7 months ago in reply to Kallikuppa Sreenivasa

Intellectual 580 points

Hi,

any input ftom the power expert?

Regards

Tom

0 Thomas Langhammer 7 months ago in reply to Thomas Langhammer

Intellectual 580 points

Hi,

any update on this?

Regards

Tom

0 Daniel Pohl 7 months ago in reply to Kallikuppa Sreenivasa

Prodigy 10 points

Hi,

any update on this?

Regards

Daniel Pohl

0 Brenda Diaz 7 months ago in reply to Daniel Pohl

TI__Mastermind 22441 points

Hi,

Thanks for your patience. I'll be taking over this E2E request. The 10ms between VDD_CORE and the 3.3V IO configured in the TPS6522053 PMIC power-down sequence was tested and validated on bench using the AM64 starter kit. For any new or custom PMIC NVM configuration we recommend following the SoC requirement "VDDSHV power rails to turn off as late as the last core supply" because we have not validated a scenario where 3.3V IO stays ON for an extended time (beyond 10ms).

The reason why TPS6522053 was configured to turn-off 3.3V IO last is because we wanted to make this PMIC configuration generic for 3.3V and 5V input supply. For example, if customers use a 5V input supply, they can replace the external power-switch with a 3.3V Buck and use the output of this Buck to supply the PMIC LDOs. Turning-OFF the 3.3V last allow customers to use this rail to supply PMIC LDOs, helping to reduce power consumption on applications using 5V input supply.

Thanks,

Brenda

0 Thomas Langhammer 6 months ago in reply to Brenda Diaz

Intellectual 580 points

Hi Brenda,

thank you for the clarification. My use case is VSYS=5V so I understand the reason for the deviation. So I think I need to take care that the 3.3V buck discharges the 3.3V rail fast enough in order to minimise the time with 3.3V still present during power off.

Regards

Tom

0 Brenda Diaz 6 months ago in reply to Thomas Langhammer

TI__Mastermind 22441 points

Hi Tom,

Yes, it is recommended to use a DC/DC with internal active discharge. For example: TPS62A0x.

Thanks,

Brenda

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AM6442: Power Down Sequence Restrictions