AM6442: How to eliminate the Gap between each transfer of GPMC?

Zekun Bai

Part Number: AM2434

Tool/software:

Customer now are testing AM243 customer board with GPMC accessing FPGA.

The mode is configured as single access with a data width of 16 bits, non-multiplexed.

From the timing point of view, there is a large gap between the completion of each read and write and the start of the next packet of data.

Now they tried modified this Bit8 and Bit11 but the gap only increase, can not decrease. With 0, Gap is 200ns, with larger cycle, gap will be larger. So how to eliminate this gap? Thanks for your help.

Regards

Zekun

16 days ago

0 Prashant Shivhare 16 days ago

TI__Guru 51271 points

The subject matter expert is currently out of office for this & next week. Please expect a delayed response.

Thanks for your patience.

0 Zekun Bai 14 days ago

TI__Intellectual 2740 points

Attach the performance benchmark from product line.

Mbps (Bits per sec)

Mode : 16 bit Address and Data Non-Mux Mode

Memory : PSRAM

Write speed: 40.9Mbps

Read speed:44.4Mbps

0 Swargam Anil 3 days ago in reply to Zekun Bai

TI__Mastermind 34930 points

Hello Zekun,

Can you please confirm the Measured results in the debug build or release build ?

If you measure results in the debug build, then try it in the release build ?

Regards,

Anil.

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AM6442: How to eliminate the Gap between each transfer of GPMC?