PROCESSOR-SDK-J721S2: SBL Configuration Issue: Duplicate Initialization in SBL1 and SBL2?

Part Number: PROCESSOR-SDK-J721S2

Tool/software:

hi，TI team，

Description:

In the current project, our boot flow is designed as follows:
SBL has been modified into two stages, SBL1 and SBL2, where the RBL initializes SBL1, and SBL1 subsequently initializes SBL2.

Currently, I am encountering an issue in SBL2 during the DDR initialization process. The details are as follows:

Functional Requirements:

• SBL1: Configures only the MCU domain R5_0 core.
• SBL2: Responsible for configuring the MAIN domain cores.

Current Issues:

1. tifs.bin Initialization:

   • In SBL1, tifs.bin has already been loaded and initialized.
   • Question: Is it necessary to reload or reinitialize tifs.bin again in SBL2?

2. DDR Initialization:

   • In SBL1, DDR has already been initialized and is functioning properly.
   • However, in SBL2, when DDR initialization code is executed again, the program hangs at the following code block, with no indication from the register values:
     

     while (regVal == 0x0)

     { regVal = HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance))) & 0x80; BOARD_DEBUG_LOG("Reg Value: %d \n", regVal); }
   • Question: Is it necessary to reinitialize DDR in SBL2? If not, how can I optimize DDR configuration in SBL2?

3. SBL2 Loading Issue:

   • When SBL2 takes control, which parts of SBL1's initialization results can be safely relied upon?

Looking forward to any guidance or recommendations. Thank you!