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L138 VPIF asynchronous output different from input

Vladimir Manannikov
Prodigy 50 points

hi,

I am using TMDSEVM L138 board  for proccessing PAL video.

The datasheet says :

"2.1 Clock Control

The VPIF has 4 clock input pins and 2 clock output pins. Each channel has 1 clock input pin with clock edge control using the CLKEDGE bit in the channeln control register (Cn CTRL). VPIF can provide a clock for an external device on channel 2 or 3 using the CLKEN bit in the appropriate C2CTRL or C3CTRL register. The clock generated by VPIF will have the same frequency as the input clock."

 However, the output video signal is "slide" relative to the input signal. That is, has a output frequency different from the input.

This creates problems when i synchronize the process of image processing and video output.
How to solve this problem?

Vladimir.

  • 0
    TI__Genius 14405 points

    Vladimir,

    What do you mean by

    Vladimir Manannikov said:
    However, the output video signal is "slide" relative to the input signal. That is, has a output frequency different from the input.

    If your input clock to ch2 is identical to input clock to ch0, and you source ch2 output clock with ch2 input clock, the ch2 out clock and ch0 in clock will be the same frequency, with a possible phase difference.

    Are you asking about the phase difference here? or are you talking about the synchronization between the blanking signals fo the input/output video?

    regards,

    Paul

  • 0 in reply to Paul.Yin
    Prodigy 50 points

    Paul,

    I'm talking about synchronization between the blanking signals of the input/output video.

    I understood the cause of the problem.
    The eval board uses a different frequency clock for inputs ch0 and ch2. One from decoder, the second - from PLL 27MHz.

    I regret that eval board designers have made a mistake ... I'll have to modify board.

    Thanks, Vladimir

  • 0 in reply to Vladimir Manannikov
    TI__Genius 14405 points

    Thank you for point this out Vladimir.