Hello
I am trying to figure out how to multiplex 8 SD channel per one VIP.
Suppose FPGA glue logic is not an issue, can it be done in the following manner:
· Using two pixel clocks per VIP and dividing the 16 bit busses into two 8 bit busses, as suggested on Table 2-6.
· Multiplex 4 channels with embedded sync and identical resolution as required on each bus.
Suppose this is possible, can each of the two 8 bit busses be configured to a different SD resolution?
If it cannit be done in that manner, is it possible at all?
thanks